Error code -84 is -EILSEQ error and is reported by the sdhci_data_irq() function from MX50 mmc host driver. If you see this error, probably a data CRC error or an end bit error has been detected by the eSDHCv3 port. I observed this error on certain eMMC parts such as Micron N2M400ED0315J60F and MTFC2GMTEA-WT. To resolve this problem, I disable the DDR mode support in SD3 and change the mmc3_data.dll_delay_cells from 0xc to 0 in mx50_arm2.c. The field dll_delay_cells adjusts the SD delay line in read path and only exists in eSDHCv3. i.e. SD3 port in MX50.
From
static struct mxc_mmc_platform_data mmc3_data = {
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
| MMC_VDD_31_32,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR,
.min_clk = 400000,
.max_clk = 40000000,
.dll_override_en = 1,
.dll_delay_cells = 0xc,
.card_inserted_state = 0,
.status = sdhc_get_card_det_status,
.wp_status = sdhc_write_protect,
.clock_mmc = "esdhc_clk",
};
To
static struct mxc_mmc_platform_data mmc3_data = {
.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
| MMC_VDD_31_32,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.min_clk = 400000,
.max_clk = 40000000,
.dll_override_en = 1,
.dll_delay_cells = 0,
.card_inserted_state = 0,
.status = sdhc_get_card_det_status,
.wp_status = sdhc_write_protect,
.clock_mmc = "esdhc_clk",
};
