Alexander Aleshkin

XCF5206 - Cyclone MAX - BDM doesn't work properly

Discussion created by Alexander Aleshkin on Apr 23, 2007
Latest reply on Apr 26, 2007 by Alban Rampon
Hardware description:
Cyclone MAX, firmware - 7.42-5.6
Board with XCF5206, which normally works (program loads from external flash and
executing ok).
Computer - Windows XP.
Cyclone connects to XCF5206 with minimum (31 – BDM SPEED FREQUENCY – 724648Hz)
speed setting using P&E In-Circuit-Debugger “Hotsync” button and synchronous cable. Memory,
disassembly and registers values are correct. “Connect” button doesn’t work, I
always got the “Can’t establish communication error…”
Coldfire CPU clock – 33MHz
Step-by-step works strange. Sometimes “step” execution is correct, with adequate
registers changes, but sometimes I got an “Error communicating to target
processor” message, and all information was lost. Executing several “step”
commands in this situation sometimes could restore normal debug (with PC to the
next instruction) or sometimes processor becomes completely unresponsive and
functioning resumes only after “reset” command. “Go” command and breakpoints don’t work.

I’ve checked signals and noticed a strange thing: RSTO regularly goes low for
short period, at about 1 time per second. I thinks that debugger malfunctioning
is connected with this, maybe it tries to communicate with processor when RSTO is
low. I’m not sure about direct correspondence, but it seems to be so.

I have several ideas about that:
1) XCF5206 is regularly reset by surrounding hardware. But RSTI is always at
3.3V, so the only way to reset processor is to power it down and then power it
up. According to MCF5206 manual this is incorrect: Master Reset requires RSTI
driven low for at least six clocks. Never the less, is such reset possible?
Should I control signals at power supply pins?
2) Processor is reset by watchdog timer. But the manual says that after reset
watchdog is disabled. Also documentation to IDC says: “Reset enables the watchdog
timer.” I confused with such inconsistency. What should I do to find out watchdog
behavior?
3) Processor has connection to DRAM module, which is onboard. Maybe resets are
initiated by DRAM controller, watchdog bus controller or something like this. I'm
not familiar with memory functioning, have just begun studying this area. What
tests should I perform to figure out such reset possibility?

Or maybe RSTO changes are normal situation during BDM session and debug problem
lays in another area?

--
Alban Edit: please include product info in subject line.

Message Edited by Alban on 2007-04-26 12:01 PM

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