Sujith Nair

Enabling PLL to get a different SCI baud rate

Discussion created by Sujith Nair on Apr 12, 2007
Latest reply on Apr 17, 2007 by Daniel Lundin
Hi,

My crystal is 20MHz and with a Bus Clock of 10MHz (osc/2), I can communicate with SCI0 at 153600 baud fine. But now I want to change it to 115200 baud and since 10MHz does not allow that (nearest integer SCIBD value results in a lot of error), I thought of using the PLL and get the desired bus clock freq.

The problem is that the PLL does not seam to be doing anything. I have re-verified the hardware design and XFC filters have been designed properly.

Below is my code (Codewarrior 4.5), please tell me if I am missing something and possibly how to know for sure that the PLL is being enabled.

 SYNR = 5;                           //to get PLL as 40MHz from a 20MHz OSC
 REFDV_REFDV = 5;           //to get PLL as 40MHz from a 20MHz OSC
 CLKSEL_PLLSEL = 1;
 PLLCTL_AUTO = 1;
 PLLCTL_PLLON = 1;
 
I have verified that CRGFLG_LOCK bit gets set to 1 indicating that PLL is within tolerable range.

1. Is there anything else I need to do inorder to get the PLL to work?
2. Will the changed PLL clock freq. change the input clock freq. to the SCI module also?

Thanks a million
Sujith

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