Omar Pighi

imx25 SRAM CS0 configuration

Discussion created by Omar Pighi on Nov 24, 2011

it seems to be a easy configuration but i cannot make it work.

I tring to configure the cs0 area to access an external 16 bit peripheral that works as a asyncornous memory. (it has also a wait# signal)

SO i configured the

Chip Select 0 Upper Control Register 0x00000787
Chip Select 0 Lower Control Register 0x00000D01
Chip Select 0 Additional Control Register 0x00000000

accessing it using a LDR istruction (writing and reading it) (32 bit access) i should have two write access (EB0 and eb1 goes low 2 time ) and during reding i should see oe goes low 2 tiems as well (accordly with the timing digrams on the ref manual).

but i have a very strange behaviour... first of all i can see just one access in wr or in read...


then i tried to add some setup and holt time ( OEA != 0 in the lower control reg)... well now i see O goes low several times .. even 16 time for each acces.....


I'm doing something very wrong... but what...

it should be a very simple set up...


i did another test and i noticed.

one more strange bahaviour, the access time during a write is related to the WSC i set (I disabled the WAIT in this test) but the read access time is much more longer.....