Ermingarda Jib

9S12XDP512 - Spurious interrupt

Discussion created by Ermingarda Jib on Mar 26, 2007
Latest reply on Mar 26, 2007 by Stephen Russell


I'm have a problem with spurious interrupt in a 9S12XDP512 processor.

I have two interrupts that some times occurs at the same time (XINT and PIT1).

Looking with the scope I realized that when they occur at the same time XINT ISR is runned and the PIT1 ISR gives me a spurious interrupt.

What can I do to make the processor run the PIT1 ISR after it ends the XINT ISR?

Alban Edit: Part number in subject line.

Message Edited by Alban on 2007-03-26 01:18 PM