Bill Scheremeta

S08QG8 - Detail BRSET/BRCLR Timing for an I/O port

Discussion created by Bill Scheremeta on Mar 22, 2007
Latest reply on Mar 23, 2007 by Bill Scheremeta
For a qg8 processor, I have this pseudo code:
bSomeBit=1 ;takes 5 bus cyles
bSomeBit=0 ; takes 5 bus cycles
1. Assuming that 'some bit is initially 0', is it guaranteed that the resulting pulse width of the bit of the i/o port is a minimum of 5 cycles. (this would not be the case on a microchip design I am porting from because of their internal decoding internal logic).
2. Anybody got a cool C macro that takes BUS_FREQUENCY as an argument and inserts assy NO-OPS after each bit assignment based on the value of BUS_FREQUENCY? (the numbers aren't important, just the macro template)
Alban Edit: added part number in subject line.

Message Edited by Alban on 2007-03-22 11:09 PM