Zigbee 13213 Footprint

[glowbrain]

Does anyone know where to get an accurate footprint for the 72 pin 13213(qfn-64). I'm using Altium, but I can convert other formats.

[ZigBeeficator]

Hello,

There is a detailed application note describing MC1321x family footprint at the address below :

http://www.freescale.com/files/rf_if/doc/app_note/AN3149.pdf

And if you download any of the 3 reference designs which are available at this address, you will have included some gerber files you my be able to reuse :

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC13213&nodeId=01J4Fs25657103#Printed...

Regards

[glowbrain]

Thanks for the reply. I have seen the documents that you mentioned, and have actually created a footprint in Altium to the specifications, but it desnt't look exactly like the ones in the reference design. I hadn't thought of converting the reference gerber files to Altium.

I just thought that it would be in Freescales best interests to release chip footprints (or in fact complete "components") to developers that wanted to use their products. If you had these components you would be more likely to choose a freescale product in the first place, and be more confident of your design before you go to manufacture.

[joerg]

Hi glowbrain
I have done the footprint recently and then, thanks to your request, i have noticed there is an applicatin note on the footprint. I am asking me why important information is not included in the data sheet?
Now i ave corrected the footprint for EAGLE it is now very similar to the on suggested by the application note, except for the shape of the pin pattern because EAGLE does not have the possibility to do rounding only on one side.

The footprint as well as the symbol is included in the -68hc.zip file and can be downoaded:

www.systech-gmbh.ch - EAGLE

Saluti Joerg

[glowbrain]

Hi Joerg,

I downloaded Eagle, and opened the unzipped file -hc68 (using File->Open->Library) and it seeed to open an empty libaray. Doing a "Zoom To Fit" says I have an empty libaray.

Any Ideas?

[joerg]

hi glowbrain
when i am downloading the -68hc.zip file and unzipping it it works. (i only messed up the file name on the eagle page [-hc68.zip instead of -68hc.zip]).

Did you copy the unzipped file into the lbr directory of EAGLE?
Usually x:/Programms/EAGLExxx/LBR

If you do not see the -68hc.lbr file your project, you have to right click on [Libraries] in the EAGLE Control Panel (top of the list) and select the "Use all" option.

Saluti Joerg

PS. to be sure i have added the -68hc.zip file on this message.

Message Edited by joerg on 2007-03-2609:14 PM

[Alban]

And here is another useful hands-on contribution from Joerg.

Thanks!

Ciao,

Alban.

[strikecity]

I worked through footprint creation w/ direct assistance from Freescale. The #1 undocumented tip is: don't just duplicate the outline of the "flag" pad on the underside of the part. Freescale apparently did this originally, and had chips float away during reflow due to the large mass of solder paste beneath the part. So, be sure to perforate the flag like they've done in their reference gerbers!

[glowbrain]

Thanks for the tip StrikeCity; but I'm not sure that I understand what you mean by perforate. Should we use hashed copper polygon? Or make the soldermask smaller than the copper? Or put via's in like Joerg?

From what I saw of the reference gerber files, I didn't see any perforations. Which one did you use?

[bigmac]

Hello,

The "perforation" would simply refer to the splitting of the flag area into eight separate rectangles, to reduce the unbroken solder paste area.

I see that AN3149 layout drawing shows the pads associated with the inner test points (pins 65 to 71).  Since these test points are for factory use only, and are totally undocumented, should these pads actually appear on the footprint?  It would seem somewhat pointless.

Regards,

Mac

[glowbrain]

I was under the impression that the centered ground pane needs to be grounded for "RF grounding" according to AN3149. Separate rectangles would still need to be connected (thereby making them no longer separate!?)

And now that I have read that section again, I see where Joerg got his reference for the "Via"'s. That was well hidden in the text, as I didn't notice that they were via's from the diagrams.

I agree that the internal pads are superflous, but while I was at it, I put them in.

[peg]

Hi,

I believe the intention here is not to break it up into 8 _completely_ seperate rectangles, they are still connected by thin traces. The idea is to prevent the solder from forming one big globule which may cause the chip to lift while still giving adequate thermal/rf protection.

On the test points, several users in their prototypes have had problems with solder shorts between these test points. Maybe this is another reason to leave them off and maybe just make a big hole here on your prototypes.

[bigskip]

I am having problems with those test points solder shorting together underneath the IC. I followed the ap note AN3149 exactly except for the TPs. I deleted the TP pads completely because i did not want to paste a pin that was inexcessible and had a potential to short together.... apparently that didn't matter - solder still found a way to flow towards them & short them out.

Has anyone tested Peg's method of routing out the board around these TPs? This was an idea brought up in a meeting I attended on "suggestions on how to solve this problem". Another idea was to reduce the stencil aperature around all the pads by 5% and around the flag by 10% or more.
Our current stencil is 5mil - possibly reducing this might help too?

Erik.

[strikecity]

I agree with both of peg's points.
1) peg's clarification of my earlier point about perforating/breaking up the flag area is exactly right. Of course the entire area remains electrically continuous, you just want to create some physical slits or breaks to keep the solder from globbing.
2) I'd sure hate to create scrap boards and/or fairly technical rework labor because of pads which you have no intention of ever using. Unless you intend to create a test fixture which monitors internal chip communications over these lines (for what purpose???), I'd leave them off. The extra pads can't possibly help you, and peg has referenced a very plausible way they could hurt.

[bigmac]

Hello,

It occured to me, whether the sub-divided pads beneath the flags really need to be joined at all?  After all, when the device is soldered in position, the flag itself will short the individual sections to each other.  Therefore the interconnecting traces would appear quite superfluous and do add complication to the footprint.

It would seem to me that the only purpose of the flag connections is to provide a low inductance and resistance connection between the flag and the ground plane layer of the board.  The via associated with each sub-division achieves this, and the presence of multiple vias will minimize the inductance and resistance of the connection.

Regards,

Mac

Message Edited by bigmac on 2007-04-0402:55 PM

[glowbrain]

Thanks Joerg. It was my ignorance of Eagle that was the problem.

The footprint looks nice. Are those "Via's" in the middle of the centre ground panes? If so, did these present any problems. Perhaps with mounting of the IC? Any reason you didn't just use some sort of poly fill?

Message Edited by glowbrain on 2007-03-2701:13 AM

[joerg]

Hi
i tried to do a ground plane with a polygon first, but this has some disadvantage when you do the DRC (design rule check) because the polygon (or rectangle) has no name and therefore no connection. Using pads has also the advantage that the solder masks are created automatically. The vias should not create problems. Actually in the application note there are mentioned two of them in the middle of each group of the pads, so i have put two vias there. I think the third one will also do no harm. My vias have 0.5mm instead of the 0.3mm proposed, but since i do not like drills smaller then 0.5mm (my milling machine destroys little drills too often) i did it this way. You can change the diameter in the library with only a few clicks.

I am actually routing the module for my HCS(08) System for the MC1321x family including the antenna, if you want i can send you the file when i have finished it. I think the challenge will be the soldering!!!


Saluti Joerg

[Alban]

Yo Joerg,

You ask a very legitimate and interesting question.

The datasheet is contractual information about the device itself.

Application Notes, Engineering Bulletins are to complement information of a device or feature detailed explainations on how to put it in action.

Very very few engineers are already reading the datasheet... We can judge by questions generally asked.

So if the datasheet was even thicker, that would certainly scare more engineers.

The datasheet for S12XE is 1000 pages.

Alban.

[bigmac]

Hello,

As a minimum, perhaps the data sheet for each device should prominently include a list of references to other directly applicable material such as Application Notes and Engineering Bulletins.  This list should preferably be identified within a separate section that appears in the Contents page.  A very brief synopsis of each reference would also be helpful.

In the case of the complex footprint for the MC13213, it would do no harm to also reference the separate document containing the drawings, in the same section as the packaging information.

After all, the primary reference in becoming familiar with the intricacies a new device is, and should be, the data sheet document.

Regards,

Mac

Message Edited by bigmac on 2007-03-2501:28 PM

[glowbrain]

Thanks for the schematic Joerg, I am downloading Eagle now and will have a look.

I didn't have any trouble finding the data sheet, but like you Joerg, I had troubles exactly duplicating the footprint. Things like rounded pads, exact polygon pour of the Gnd pads under the chip, and things like that.

Freescale have obviously alerady created a footprint for the IC, so why don't they have this for download? Having each customer re-invent the wheel by reproducing the footprint is prone to error, and is of course wasted effort.