Matthew Hilder

MX35 IPU ADC autorefresh

Discussion created by Matthew Hilder on Oct 6, 2011
Latest reply on Oct 10, 2011 by Matthew Hilder


I have a simple mono graphic display on ADC display 0 using SYS2_MODE = 7, i.e. write in command buffer mode.

I have loaded the DMA channel parameter RAM for ADC DMA channels 3 and 5 with appropriate values and all works fine for core triggered DMA, i.e. ADC3_SRC_SEL = 0.  The core triggers the DMA by writing the buffer 0 ready bits for channels DMAADC_3_BUF0_RDY & DMAADC_5_BUF0_RDY.

If I now decide to switch to autorefresh using ADC3_SRC_SEL = 6 then the refresh does not work unless the core keeps setting DMAADC_5_BUF0_RDY which rather defeats the point.

It appears that autorefresh mode correctly sets DMAADC_3_BUF0_RDY at each refresh interval but forgets about DMAADC_5_BUF0_RDY, i.e. autorefresh will work in any of the template modes that only use DMAADC_3 but won't work in command buffer mode.

The reference manual clearly states that SYS2_MODE = 7 is valid for autorefresh.  My set-up doesn't agree.


Has anyone else seen this?

Is it working for you and it's just me?