Alexandre Kremer

52233 and QSPI

Discussion created by Alexandre Kremer on Mar 8, 2007
Latest reply on Mar 14, 2007 by Srikar Thaduvayi
 Hi all
 
 I´m working with MCF52233 and it´s QSPI interface.
 The code below was written to make the QSPI send 7 times a 16bit data of (0xFFFF) and 1 time a 16 bits data of (0xFFFE) continuously (Wraparound enabled).
 I see it is sending those words of data continuously right, eg the SDO line is 3.3V during 16 SCLK pulses * 7 times it must send 0xFFFF, but at the end of the information (when it sends 0xFFFE) right after the last of the 16 SCLK pulses (when the SDO line is already low because the 0x FFFE) there are more 8 SCLK pulses that shouldn´t be there in my opinion. Right after those 8 SCLK pulses, the SDO line goes high again to the next round of 7 0xFFFF and 1 0xFFFE.
 So the chip is really sending 7 times 0XFFFF and 1 time 0XFFFE, but after this the SCLK line has 8 pulses more.
 Im my opinion, right after sending 0xFFFE the mcu should put the SDO line high and then start driving the 16 SCLK pulses for the next round of 8 16 bit transfers.
 
 Can someone help me with this? What can i be possibly doing wrong?
 
 Also, when i put this same code to run on Coldfire_Lite.mcp (yeah, this one with the http server), the signals start flowing right but suddenly the QSPI stops. Checking the QSPI registers, i see some function messed up with QMR value and the QIR, wich has to be 0x0001 (SPIF set only) has 0x0005 (SPIF set and WCEF set) indicating there was a colision. Since my code doesn´t write on QMR register anymore, some other code is writing to this it.  Does somebody knows who is messing with QMR or if there are registers ambiguity declarations?
 
 Thank you
 
 Regards
 
Code:
void qspi_init(void){/* Enable QSPI Pins Primary Functions */ MCF_GPIO_PQSPAR |= 0x1555;  MCF_QSPI_QMR = 0xC04B;  /* set up delay from chip select to first edge of QSPI clock */ MCF_QSPI_QDLYR = 0x0000; MCF_QSPI_QIR |= MCF_QSPI_QIR_SPIF;  /* Make sure SPIF is cleared */}                //reg_SPIDR; void qspi_init_cs5532(void){ /* set queue pointer to the first command RAM entry */   MCF_QSPI_QAR = 0x0020;  /* command entry for transfer to QSPI_CS0 */ MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00; MCF_QSPI_QDR = 0xCE00;  /* set queue pointer to the first data RAM entry */ MCF_QSPI_QAR = 0x0000; /* data RAM entry for transfer to QSPI_CS0 */ MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFF; MCF_QSPI_QDR = 0xFFFE; /* set up wrap register for 8 16-bit transfers */ MCF_QSPI_QWR = 0x7800;    /*start the transfer */  MCF_QSPI_QDLYR |= MCF_QSPI_QDLYR_SPE; }

 

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