MC9RS08KA2 voltage comparisons

[jackabo]

I am working on a project where I have placed two resistors in series and placed a wire between those resistors that connects to my PTA0. Depending on the voltage between those resistors, I want to set my A register to a certain value. Does anyone know how this can be done. I don't want to use the ACMP- and ACMP+ comparison since I don't have a value that would be coming from PTA1 to compare my PTA0 to. And I don't think i can use the internal bandgap reference voltage since it is only 1.2 V, according to the specs. Does anyone know of another way to do this? I need to have values for 3.3V (which is my VDD), 1.6V, and 0V. If it were only 3.3V and 0V I would think it would be easier since I can just check if logical value of the pin is either 1 or 0. If anyone could get me some suggestions I would really appreciate it. Thanks.

   Jackabo

[peg]

Hi jackabo,

Refer to AN3266 for a fully documented method to do exactly this. It has code and calibration methods and everything.

[bigmac]

Hello Peg and Jackabo,

The method described in AN3266 is actually the one that requires a regulated Vdd.  So it could not be used to measure Vdd in the case of battery operation without a regulator.

The method described in my previous post is actually slightly different.  While having inferior linearity and other limitations, it does permit Vdd to be measured.  While the original post was a little unclear in this respect, my interpretation was that this might be required.

Regards,

Mac

[bigmac]

Hello again,

I have now had a closer look at AN3266, and while I do not have argument with the basic method, I would disagree with some of the assumptions made in setting up the arrangement.

Primarily, I would take exception to the assumption of an input voltage range of up to 99 percent of Vdd.  This gives extreme non-linearity of the voltage ramp, that effectively reduces the available resolution to somewhat less than 6-bits, at low input voltages.

However, if the input voltage range is restricted to somewhere between 50 - 75 percent of Vcc, using an input voltage divider as necessary , the non-linearity will be significantly reduced.  This will result in a substantial improvement of overall resolution to 7-bits (including the effect of the input voltage divider).

In either case, a 256 byte look-up table is utilised by the firmware to compensate for non-linearity of the conversion, but in the latter case this gives the higher resolution, so there is much more efficient use of this data overhead.

Assuming a 4us timer increment is retained, and there is a maximum limit of 75 percent of Vdd, the time constant of the CR network producing the ramp would be increased from 220 us to 700 us.  The maximum measurement interval would remain at about 1 ms.  The present circuit uses resistance value of 4k7  - I believe a value of 47k would be far more appropriate, with a capacitor value of 15n to give 700 us.

In addition, there appears to be a far better way to provide for calibration of the converter, to compensate for component tolerances and for Vdd variation.  This is to periodically take a measurement using the internal band gap reference, and use the value obtained to compensate for the calibration errors during the normal measurements.  However, this calibration will require additional integer multiplication and division processes to calculate the corrected value, properly sequenced so that there is no reduction of resolution of the final result.

Regards,

Mac

[jackabo]

I have been working on a A/D conversion using the ACMP+ and ACMP- on my MC9RS08KA2 on a Softec board. I have aksed questions about this before and in one of the responses someone said that they "would take exception to the assumption of an input voltage range of up to 99 percent of Vdd." They said that using a range of 50-75% of Vdd would be more accurate. I used code based on the RSO8 Peripheral Module Quick Reference. My question is if there is anything I can do to make me be able to accurately translate an input voltage range up to Vdd? Right now I am getting a digital value of 215 for Vdd instead of 255 as it should be. Thanks for the help.

Jackabo

[bigmac]

Hello Jackabo,

Firstly, I suggest that this thread is really a continuation of the earlier  thread about your A/D problems, and might have been better handled as such.  The following link is to the earlier thread.

http://forums.freescale.com/freescale/board/message?board.id=8BITCOMM&message.id=5035#M5035

What I did say then was, that a reduction of the input voltage range (to the comparator) would result in much improved linearity and resolution.  This is not quite the same as accuracy.

The use of the lookup table, within the AN3266 code example, is to compensate for the non-linearity of the voltage-time characteristic of the CR circuit.  Refering to the contents of the table, you will see that the first steps are 0, 5, 10 ...   At the end of the table there are ten entries with the value 253.  This represents substantial non-linearity, and with the initial steps of 5, this gives a resolution of 5/255 (less than 6-bits) for low input voltages, where high resolution is most important.

As previously outlined, the non-linearity can be reduced, and the resolution significantly increased by reducing the maximum  voltage applied to the comparator input.  However, to achieve this the time constant will need to be increased, as previously discussed, and the lookup table values would need to be re-calculated to cater for the reduced non-linearity over the new input voltage range.

To cater for higher measured voltages (perhaps in the vicinity of Vdd, or even higher), you would need a voltage divider to reduce the input range down to the comparator input requirement.  The scaling of the divider will directly affect the calibration of the measurement.

Note that this method uses Vdd as a "reference", so you cannot actually directly measure Vdd voltage (it is assumed that Vdd would be fed from a regulator).  For cases where Vdd is supplied from an unregulated battery source, a different strategy would be required.

An alternative scenario - if the capacitor were to be fed from an accurately controlled, external constant current source, rather than a resistor, the voltage-time characteristic would be linear, and the lookup table would not be necessary.  If the constant current were to be independent of Vdd, you could actually measure the Vdd voltage (still using an appropriate input voltage divider).

Regards,

Mac

Message Edited by bigmac on 2007-04-1203:36 PM

[bigmac]

Hello Jackabo,

Unfortunately, the device you are using does not contain an ADC module, so you are stuck with using the comparator.

Provided you don't need too much accuracy, you might be able to implement what is known as "single ramp" A/D conversion.  This would require a capacitor to be connected between the ACMP- input and ground, and a resistor is provided to charge the capacitor.  The other end of the resistor would connect to the voltage to be measured.  The band gap reference would be enabled at the ACMP+ input.  You will also need to use the MTIM module to measure the elapsed time for the capacitor to charge to the reference level.

Before the start of a measurement, the ACMP- pin would be set as GP output, with a low level, so as to discharge the capacitor.  To initiate a measurement, the ACMP- input would be activated, and the timing would commence.  The capacitor will begin to charge at a rate determined by the applied voltage, and when the capacitor voltage reaches the reference level, the comparator output will change state and terminate the time measurement.  The pin can then again be set as GP output ready for the next reading.  You will probably need to use a lookup table to relate elapsed time to the input voltage value.

This simple method has accuracy limitations, it cannot measure voltages lower than the 1.2V reference, and the relationship between elapsed time and voltage is very non-linear.  You will need to scale the resistor and capacitor values to suit the setup of the MTIM.  These should be close tolerance components.

Another configuration is possible that would provide a more linear relationship, but would also require a regulated Vdd supply.

Regards,

Mac