Debugging COP resets...

Discussion created by BILL WESTFIELD on Feb 26, 2007
Latest reply on Feb 28, 2007 by BILL WESTFIELD
I was having a tough time debugging some COP reset issues using the
black widow virtual lab, and I think I finally figured out that this
was because a COP reset resets the Background Debug System as well as
the rest of the CPU. Since things like breakpoints are done via
registers in the BDC, they all disappear when a COP (or other) reset
occurs. So all the careful breakpoints I put in early init code trying
to catch a reset occuring got essentially deleted by the reset. Sigh.

So how do you debug COP reset issues? Can the BDC be configured to
trap resets automatically (I skimmed that section of the manual and
didn't see anything)? Can I force the debugger to insert "hard" code
style breakpoints (that survive a cpu reset) instead of using the BDC
hardware breakpoints or trap resets that happpen during debugging?
(some of my pain was from expecting patched-code style breakpoints,
which I'm used to on large CPUs...) The DBG module has the same
problems as the BDC, doesn't it?