Ken Johnson

5475 branch cache causing instruction fetch from invalid memory

Discussion created by Ken Johnson on Feb 22, 2007
Latest reply on May 15, 2009 by Yingjian Zhan
My 5475 system has no memory mapped at 0x00000000. If I invalidate and then configure data, instruction, and branch caches, the following code (with full optimization) causes an instruction fetch from address 0x00000000 (which causes an XLB Arbiter timeout.) If the branch cache is not enabled, no instruction fetch from address 0x00000000 occurs:

------ example code ------
typedef void (*tFuncPtr)(void);
void f1( void ){

tFuncPtr ftable[]={

void Test( void )
tFuncPtr s, *p;

if (!(p = ftable)) return;

for ( ; (s = *p) != 0; p++)

------ end example code ------

Is there any way to prevent the branch cache from fetching instructions from invalid memory?

The CACR and ACRs are configured as follows on my 5475 system:

CACR = 0x84088400
ACR0 = 0x601C0020
ACR1 = 0x7007C400
ACR2 = 0x6001C000
ACR3 = 0x9001C000