Richard Serge

IIC Status Register... WTF?

Discussion created by Richard Serge on Feb 17, 2007
Latest reply on Feb 18, 2007 by Richard Serge
S908GT32A, 14.68Mhz bus, IIC Clock rate divider=7 (div by 40) = 370KHz IIC clock

Ok, before I get into any serious code for the IIC module I thought I'd have a look at what goes on in the status register (since the data sheet just confused the crap outa me). I wrote the code below to do that. It just generates a start condition and sends an address byte out to nowhere (since I have no device at address $CC). I specifically wanted to know when the TCF bit (7), the BUSBUSY bit (5), the IICIF bit (1) and the RXAK bit (0) would become set.

               LDHX           #$100
               MOV           IIC1S,X+        ;WHAT IT IS B4 WE FOOL WITH IT.
               MOV           #%10110000,IIC1C  ;IICEN+MST+TX = START CONDITION.
               MOV           #$CC,IIC1D      ;SEND ADDRESS BYTE.
SAVSTAT        LDA           IIC1S           ;3
               STA           0,X             ;2 SAVE STATUS REG.
               AIX           #1              ;2 FROM $100 AND UP.
               STA           SRS             ;4 (DO THIS THE LONG WAY AND
               CPHX          #$800           ;3 CONSUME EXTRA TIME TO REDUCE
               BLO           SAVSTAT         ;3 THE NUMBER OF DATA POINTS.)
                                             ;= 17CYC * 68nS = 1.16uS/loop
               NOP                           ;BREAKPOINT HERE.


The status register is written to the buffer every 1.16uS, and here it is:

00 Reads 00 before I do anything to the IIC.
00 Reads 00 immediately after getting it started.
80 TCF set after a few microseconds.
A0 Then BUSBUSY a uS later.
21 TCF cleared (huh?), RXAK set (huh?)
25 SRW set
25
25
25
24 RXAK cleared at 12 uS (?).
24
24
20 SRW cleared.
20
21 RXAK set, again!
21
21
25 SRW set, again.
25
24 RXAL cleared, again.
24
20 SRW cleared, again.
20
20
21 RXAL set yet again.
A3 TCF set, IICIF set after 30uS.
A3...A3 to end of buffer.

Kinda makes me wish I hadn't done this now, since I'm more confused than ever. Does anyone have any clues as to what's going on here?

But this is the kicker... even though I have it set for a 370KHz clock, the actual clock rate is 100KHz as seen on a scope. The IICIF bit is becoming set as though it was transmitting at 370KHz (30uS for 9 bits, + or -), but it's not. I'm lookin at it, and it's 100KHz. Start condition + 9 bits in 93uS.

If I reduce the IIC clock down to 50KHz (ICR=$24, divide-by = 288), I get TCF and IICIF both set after 56uS, but the IIC clock this time really is 50KHz, which means the byte isn't finished sending for 190uS (as seen on a scope). So why is TCF and IICIF becoming set way before the byte is complete?

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