David Lundquist

Watchdog Timer Timout Reset or Interrupt Config

Discussion created by David Lundquist on Feb 8, 2007
Latest reply on Feb 10, 2007 by Mark Butcher
I've come across what looks like conflicting info in the reference manual regarding the outcome of a watchdog timer timeout. Seems to show up even in the current revision 4 of the docuement.

If you read the text of Section 13.5.4 it states that "...resulting in a watchdog timer interrupt or hardware reset, as programmed by CWCR[CWRI]". This sounds like we have a choice in the outcome based on the set value of this bit.

If you then go to Table 13-6 on the next page which describes the bits in the CWCR register it assigns the following meanings to the CWRI bit.

0 If a timeout occurs, the CWT generates an interrupt to the processor core....

1 Reserved. If a 1 is written, undetermined behavior will result.

So, it seems that what looks like the option to select a hardware reset is invalid or not working? There is a note about using the interrupt to to generate a "soft reset" It almost sounds like this is a workaround for the hardware reset not functioning? Can anybody shed some light on this?

Thanks,
Dave Lundquist

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