Leo Schwab

Long Timers: How To Ensure Coherency

Discussion created by Leo Schwab on Feb 1, 2007
Latest reply on Feb 4, 2007 by bigmac
We have an application requiring fine-grained, long-duration timers. As such, we need to maintain a 32-bit tick count. The obvious implementation is to have an ISR handling overflows from TPMCNT, and then to read the entire 32-bit count as follows:
seilda TPMCNTLsta ticks+3lda TPMCNTHsta ticks+2lda TPM_overflow+1sta ticks+1lda TPM_overflowsta tickscli

The problem is between the 'sei' and the 'lda TPMCNTL'. It's conceivable that TPMCNT could overflow between those two instructions. TPM_overflow will then need to be incremented, but it won't because of the 'sei', making the lower 16 bits incoherent with the upper 16 bits. Swapping the instructions doesn't fix it; it just changes the "polarity" of the vulnerability.

Anyone know how to do long timers reliably?

Schwab

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