BILL WESTFIELD

XCLK on QG4/8

Discussion created by BILL WESTFIELD on Jan 27, 2007
Latest reply on Jan 28, 2007 by BILL WESTFIELD
Ok, I read the datasheet, I looked at AN3041, and even some of the code
exmaples, but I'm still confused.
XCLK is the "fixed frequency clock" selectable as inputs to the timers,
and is apparently typically lower in frequency than the bus clock. But
where does it come from and what's its value on these chips with fancy
clock circuitry? Is it the same as the internal reference clock (~32kHz?)
Is it a divided version of the bus clock? The only docs for the source of
xclk was figure 1-2 in the datasheet, and i didn't find it helpful. All
other mentions of xclk describe how it is selected as an input for the
assorted timers and such.

Thanks
Bill W

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