Sendhilraj T

36 bit physical addressing in e500v2 core using CW 8.6

Discussion created by Sendhilraj T on Jan 15, 2007
Latest reply on Jan 25, 2007 by Pascal Irrle
Hi,
I am using CW 8.6 ,patched for PQ III MPC8548.
I am trying to use the 36 bit physical addressing available in MPC8548. To avail this facility, I want to use the 16 entry TLB1 array available in the memory unit , which could be used to access the MAS7 registers.
I want to access a memory region between 0x800000000 - 0x80FFFFFFF.
The config settings that I have done for the SPRs are as below.

writespr    624 0x10070000    
writespr    625 0x80000900    
writespr    626 0x00000008    
writespr    627 0x0000003f    
writespr    1008 0x00000080

With these configurations I am not able to access the MAS7 registers......
For example ,I would like to know the configuration settings that I should do, access the memory region between 0x800000000 - 0x80FFFFFFF.

I would like to know where I should write the higher order nibble in my configuration code.
Also I would like to know what are all the configuration settings that I need to do to use this 36 bit physical addressing option available in e500v2 core.
 
Looking for your help

 T.Sendhilraj

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