danix

i.MX23 and DDR SDRAM routing

Discussion created by danix on Mar 5, 2011
Latest reply on Dec 18, 2011 by Manu Martinez

Hey all,

 

I'm designing a custom board with i.MX23 and micron DDR as in the EVK reference schematic from freescale...

 

I routed all the high speed signals (D00-D15, DQM[1..0], DQS[1..0], clk and clkn) only on bottom and top and matched the number of vias i used as in the application note, but my worry is that to what extent

is matching the trace length acceptable. In my design the longest trace is 27mm  (which is physically impossible to decrease in my layout). should all the rest be strictly matched or what tolerance is acceptable (I have traces as short as 21mm)?

 

I'm just waiting a response to continue,

thanks

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