Mark Butcher

M5223X Internal Flash Speculation Address Qualification Incomplete - Workaround 2

Discussion created by Mark Butcher on Dec 31, 2006
Latest reply on Apr 5, 2007 by Mark Butcher
Hi All

I am testing the workarounds to avoid the problem as described in the Errata Rev. 1, 11/2006 but am experiencing a problem with Workaround 2.

Here it is necessary to justify the FLASH to the lower address range of a 256k block and the SRAM to the upper 32k of the same range. I am trying with SRAM at 0x20038000..0x2003ffff.

The problem which I have is that it doesn't seem possible to have the interrupt address vectors in SRAM any more since the VBR can only be aligned to 1 Meg boundaries. To put the SRAM where I need it according to the workaround and also have the vector table in SRAM, the VBR would have to support alignment also at a 32kb boundary. This doesn't work due to the fact that the Coldfire doesn't implement the lower 20 bits of the VBR.

Question is - is this a non-mentioned restriction when using the workaround or is there some way out of the predicament?

Any one out there with the answer??


Mark Butcher