Russ Ether

lost interrupts and/or priority inversion

Discussion created by Russ Ether on Nov 25, 2006
Latest reply on Nov 26, 2006 by bigmac

Can someone please review this and offer opinion on whether my understanding is correct?

First I need to set up the problem before I can ask the question:
 
1) MC9S08DZ60
 
2) two active interrupts, call them Int1 and Int2, one occurring approximately 10 times faster than the other (Int1 faster than Int2)
 
3) Int1 is serviced by ISR1, and Int2 is serviced by ISR2

Question:  Are the following statements true?
 
ISR2 worst-case execution time must never exceed the Int1 period, or else Int1 interrupts will be lost.   This is because more than one Int1 will occur while ISR2 is executing.  The first Int1 will be pending (waiting for ISR2 to complete), but there is no provision in this chip to queue the second one - it will be effectively lost.
 
This problem could be solved by coding ISR2 to enable interrupts at the beginning.  But the problem with this is that not only would Int1 be allowed to interrupt, but also any other slower or lower-priority interrupt - resulting in priority inversion.
 

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