Hello Ester,
With Pingu's explanation, there should never be more than a difference of one between the two counter values. Is this what you observe? The count rate should be the same for both, however both counter values cannot simultaneously increment.
Note that the PWM output signals associated with each TPM module should remain synchronous within a few bus cycles, since these are determined by the timer hardware within the MCU.
It probably does not apply to your simple sample code, but there would need to be a further consideration for the more general case. Since you have set the timer modulo value to give an overflow period of 201 cycles for each module, this would require that the two timer overflow ISRs, plus any other ISR that may possibly occur, must all be able to execute in somewhat less than 201 cycles in total. Otherwise, this would lead to erratic operation of the software counters. In many instances, meeting this limit would not be possible.
Regards,
Mac