Major Typo Error?

[Fabrico]

Reading page 14 of AN2287:

Multiplexed Data Bus (PORTA and PORTB)
Internally HCS12 Family devices have full 16-bit data paths. But, depending
upon the operating mode, the external data bus may be 8 or 16 bits.
In external wide modes, the 16-bit data bus is made up of ports A and B.
• Bidirectional PORTB[7:0] shares functionality with the low byte of the
data bus DATA[7:0] and low byte of the address bus
• Bidirectional PORTA[7:0] shares functionality with the high byte of the
data bus DATA[15:8] and high byte of the address bus
In external narrow modes, the 8-bit data bus is made up of port A only.
• Bidirectional PORTA[7:0] shares functionality with the low byte of the
data bus DATA[7:0] and high byte of the address bus
• Data accesses are split into two consecutive 8-bit accesses so only port
A is used as the data bus. In this case, the external data bus does two
consecutive 8-bit accesses to handle 16-bit data requests from the
MCU.
NOTE: Back-to-back writes will not negate the R/W signal.

That should be a mistake in that the low byte of the data bus is shared with the low byte of the address bus,  not the high byte.

If the statement in the application note is true and all other references in all the other documentation from Fresscale, specifically on pinout diagrams, are false, that explain why my board will not start.

Fabrico

[imajeff]

You know that is only in "narrow" bus mode, right? I think it is pretty commonly known that the 8-bit data is shared with PortA and ADDR8 through ADDR15. So no typo. All other documents I have seen agree, esp. Figure 1-1 in MC9S12DP256B Device User Guide. It shows "Multiplexed Narrow Bus" with [DATA7..DATA0] right under PTA (which is also shown as [ADDR15..ADDR8]) One advantage to me could be that I can use an 8-bit block of addresses on [ADDR7..ADDR0] and require no de-multiplexing with the Data bus.

[Fabrico]

What about this picture?

[imajeff]

You should easily see that your diagram for the DJ64 is correctly showing the physical pinout for expanded wide mode. It would not be practical for this diagram to show both wide and narrow modes since two pins would the same symbol (D0, D1, etc.), so this pinout diagram is only intended to show physical pin mapped to logical function.

To see all the possible modes of a given pin, refer to other diagrams such as Figure 1-1 (pg.23 of the Device User Guide). Also look at S12MEBIV3 Reference Manual.

http://www.freescale.com/files/microcontrollers/doc/data_sheet/9S12DJ64DGV1.pdf
http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12MEBIV3.pdf

[Fabrico]

Imajeff,

Thanks. This explains the data bus contention I had, in details. My first board design worked without a flaw. This one has been peppered with mistakes. Does age play a role?

By the way, when the CPU starts, it tries to read the RESET vector at FF03h, any idea why?

Regards,

Fabrice

Message Edited by Fabrico on 2006-11-2902:10 AM

[imajeff]

I've never seen that problem. How did you confirm that it reads the RESET vector from 0xFF03 ?