Wong Mun Lai

MCF5235 to SDRAM interface problem

Discussion created by Wong Mun Lai on Nov 14, 2006
Latest reply on Nov 15, 2006 by Wong Mun Lai
Hi,
we have a board with MCF5235 coldfire connected to a
128Mbit Sdram (ELPIDA EDS1216AGTA 8M words x 16 bit) chip. It is connected with the
following configurations:
16-bit Port,9-Column Address
MCF5235 Pin - A16 A15 A14 A13 A12 A11 A10 A9  A18 A19 A20 A21  A22  A23
SDRAM Pin   - A0    A1   A2   A3   A4   A5   A6   A7  A8   A9   A10 A11  BA0  BA1
where BA0,BA1 are the Bank Select Addresses
We then run our Pemicro ICDCFZ_PRO BDM debugger
to initialise the registers:
/********Start Of Script**********/
;;;;;;;;Clock module Chapter 7
;Crystal Frequency = 13.56MHz
;Sets the Core Frequency = 10 * 13.56MHz =135.6MHz
;Internal Bus Frequency = 67.8MHz
MM.L 0x40120000 0x03000000
DELAY 100
;;;;;;;;GPIO module Chapter 12
;A[23:21] pin configured for address bit 23-21
;D[15:0] pins configured for data 15-0 functions
MM.B 0x40100040 0xE0
;Only CS1 pin is configured for CS function
;The rest of CS pins are used for GPIO functions
MM.B 0x40100045 0x02
;SD_WE pin configured for SDRAMC WE function
;SD_CAS pin configured for SDRAMC CAS function
;SD_SRAS pin configured for SDRAMC SRAS function
;SD_CKE pin configured for SDRAMC CKE function
;SD_CS pin configured for SDRAMC CS function
;CS2 abd CS3 are NOT configured for SDRAMC function
MM.B 0x40100046 0x3F 
 
;;;;;;;;;; SDRAM module Chapter 18
;Refresh Timing = 6 clocks
;Refresh Count = 0x42
MM.W 0x40000040 0x0242
;set RAM base address to 0x10000000
;CBM set to 3
;CASL set to bit value 01
;set Port Size 16 bit
MM.L 0x40000048 0x10001320
;set RAM base address mask to allow for 16M range
;set bit V to initialize registers controlling DRAM block
MM.L 0x4000004C 0x00fc0001 
;set IP bit to initiate Precharge All command
MM.L 0x40000048 0x10001328
DELAY 10

; Write to SDRAM to initiate precharge
MM.L 0x10000000 0xA5A59696
; Turn On Refresh Enable bit
MM.L 0x40000048 0x10009328
DELAY 1
;Initiate Mode Register Set command
MM.L 0x40000048 0x10009368
;Write to the SDRAM Mode Register
MM.L 0x10000400 0xA5A59696
/********End Of Script************/
 
Here is the error log:
 
/************Start of error log*****************/
>;;;;;;;;Clock module Chapter 7
>;Crystal Frequency = 13.56MHz
>;Sets the Core Frequency = 10 * 13.56MHz =135.6MHz
>;Internal Bus Frequency = 67.8MHz
>MM.L 0x40120000 0x03000000
>DELAY 100
Delaying for 100mS ... Done.
>
>;;;;;;;;GPIO module Chapter 12
>;A[23:21] pin configured for address bit 23-21
>;D[15:0] pins configured for data 15-0 functions
>MM.B 0x40100040 0xE0
>
>;Only CS1 pin is configured for CS function
>;The rest of CS pins are used for GPIO functions
>MM.B 0x40100045 0x02
>
>;SD_WE pin configured for SDRAMC WE function
>;SD_CAS pin configured for SDRAMC CAS function
>;SD_SRAS pin configured for SDRAMC SRAS function
>;SD_CKE pin configured for SDRAMC CKE function
>;SD_CS pin configured for SDRAMC CS function
>;CS2 and CS3 are NOT configured for SDRAMC function
>MM.B 0x40100046 0x3F
>
>;;;;;;;;;; SDRAM module Chapter 18
>;Refresh Timing = 6 clocks
>;Refresh Count = 0x46
>MM.W 0x40000040 0x0242
>
>;set RAM base address to 0x10000000
>;CBM set to 3
>;CASL set to bit value 01
>;set Port Size 16 bit
>MM.L 0x40000048 0x10001320
>
>;set RAM base address mask to allow for 16M range
>;set bit V to initialize registers controlling DRAM block
>MM.L 0x4000004C 0x00fc0001
>
>;set IP bit to initiate Precharge All command
>MM.L 0x40000048 0x10001328
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
Not ready response from chip - try a RESET.
/************End of error log*****************/
As you can see from the error log,
it always produce the "Not Ready from Chip" error when we
set DACR0's IP bit. We are unable to solve this problem.
We always have to do a reset at this point
so that we can use our BDM again.
 
OK here's the puzzling part:
if we change the following lines in the script (to WRONGLY configure
it as a 32 bit port), the register
initialization works:
/******modified scipt*********/
;;;;;;;;GPIO module Chapter 12
;A[23:21] pin configured for address bit 23-21
;D[15:0] pins configured for data 15-0 functions
MM.B 0x40100040 0xE1 ;<----modified to 32 bit port
.
.
.
.
.
;set RAM base address to 0x10000000
;CBM set to 3
;CASL set to bit value 01
;set Port Size 16 bit
MM.L 0x40000048 0x10001300 ;<----modified to 32 bit port
;set RAM base address mask to allow for 16M range
;set bit V to initialize registers controlling DRAM block
MM.L 0x4000004C 0x00fc0001 
;set IP bit to initiate Precharge All command
MM.L 0x40000048 0x10001308 ;<----modified to 32 bit port
DELAY 10

; Write to SDRAM to initiate precharge
MM.L 0x10000000 0xA5A59696
; Turn On Refresh Enable bit
MM.L 0x40000048 0x10009308 ;<----modified to 32 bit port
DELAY 1
;Initiate Mode Register Set command
MM.L 0x40000048 0x10009348 ;<----modified to 32 bit port
;Write to the SDRAM Mode Register
MM.L 0x10000400 0xA5A59696
/*******End of Modified script*****/

Now, with the modified script, we don't see
the "Not ready response" anymore. However, we see a problem
when we write to SDRAM adress 0x10FFFFFF with, say,
a value of 0x99
 
SDRAM locations:
0x10FFFFFF = 0x99(correct)
0x10FFFFFA = 0x99(wrong)
0x10FFFFF7 = 0x99(wrong)
0x10FFFFF3 = 0x99(wrong)
....and many other locations all the way to 0x10FFFFD3......
 
Many other locations got wrongly written as well. This error is
understandable since ours is actually a 16-bit port.
 
So our question is:
1) Why, in our orginal 16-bit script, the board always
go haywire when we set DACR0's IP bit?
2) Why the register initialization went smoothly when we WRONGLY
configure it as a 32-bit port?
 
 
Thanks in advance for any help given!
rgds,
Mun Lai

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