Al Char


Discussion created by Al Char on Nov 10, 2006
Latest reply on Nov 12, 2006 by Al Char
Design: 16GTA (or 32A), 32.768KHz crsytal

I go to an FEE configuration, cranking up BUSCLK to 16.77MHz. All is fine. TIM1 is then set to use BUSCLK as the source. Fine. TIM1 modulo is set to (for example) to 0x3fff, and the ISR toggles a port bit for frequency monitoring. [This needs to be VERY precise, and is being measured by a super-duper test rig.]

Since my ISR pin toggle acts as a further divide-by-two, the output pin should see 512 counts per second. The reality: 511.77, very steady, and nowhere near good enough. I can "dail" it in by decreasin the modulo value, but why would this be necessary? And would the same value carry across to ALL chips?

Perhaps I don't understand something basic about the PLL, but shouldn't a multiply by a power-of-two, followed by a divide by a power-of-two, yield a.... power-of-two? Is there some internal analog magic injecting an unwelcome contribution?

In parallel I have the RTI going, clocked from the crystal, and its ISR is toggling a different pin, also for accuracy measurements. With some particular pre-scaler value chosen I see a count of (for example) 128.001, which is acceptable.

Another problem, yet to be investigated: if I shut down (or never use) the PLL and use FBE the RTI period goes way off. Is BUSCLK needed, somehow gating edges of the RTI, therfore needing to be a MULTIPLE of the XTAL freq? I dunno. Details to follow when I get back to the office and horse around some more.

Any thoughts or advice?