GT16 PLL

[Geezer]

Design: 16GTA (or 32A), 32.768KHz crsytal

I go to an FEE configuration, cranking up BUSCLK to 16.77MHz. All is fine. TIM1 is then set to use BUSCLK as the source. Fine. TIM1 modulo is set to (for example) to 0x3fff, and the ISR toggles a port bit for frequency monitoring. [This needs to be VERY precise, and is being measured by a super-duper test rig.]

Since my ISR pin toggle acts as a further divide-by-two, the output pin should see 512 counts per second. The reality: 511.77, very steady, and nowhere near good enough. I can "dail" it in by decreasin the modulo value, but why would this be necessary? And would the same value carry across to ALL chips?

Perhaps I don't understand something basic about the PLL, but shouldn't a multiply by a power-of-two, followed by a divide by a power-of-two, yield a.... power-of-two? Is there some internal analog magic injecting an unwelcome contribution?

In parallel I have the RTI going, clocked from the crystal, and its ISR is toggling a different pin, also for accuracy measurements. With some particular pre-scaler value chosen I see a count of (for example) 128.001, which is acceptable.

Another problem, yet to be investigated: if I shut down (or never use) the PLL and use FBE the RTI period goes way off. Is BUSCLK needed, somehow gating edges of the RTI, therfore needing to be a MULTIPLE of the XTAL freq? I dunno. Details to follow when I get back to the office and horse around some more.

Any thoughts or advice?
Al

[bigmac]

Hello Al,

If your bus clock is actually 16.7700 MHz, and with your timer modulus setting of 0x3FFF, you should indeed measure an output frequency of 511.77Hz.  For an output frequency of exactly 512Hz, the bus clock frequency would need to be 16.7772.. MHz.  Alternatively, you would need a timer modulus setting of 16376 (0x3FF8).

If the bus clock should be 32768*512 (16.77216 MHz), but isn't, this may be due to oscillator frequency error - do you trim the crystal?  The error you indicate would amount to 430ppm.  You may also need to check whether the nominal capacitive loading that you apply to the crystal conforms with its specification, and also the specified initial frequency error tolerance.  Also note that these crystals will generally have inferior temperature stability compared with higher frequency crystals.

Regards,

Mac

[Geezer]

Hiya, Mac-

The XTAL showed as 32768.xyz Hz (I don't recall the exact .xyz) in the lab, whereas a 430 ppm error to explain the PLL behavior says it should have been closer to 32754+ Hz. We're much closer than that.

No way for me to measure the exact BUSCLK, as you know. Wish I could. But indeed it **should** be 512*32768 Hz.

Thanks a bunch for looking into this.

Al

[peg]

Hi,

The nearest buss frequency you can achieve with FEE and a perfect 32.768kHz xtal is 16.777216MHz

and a value of $3FFF in the modulo register should give you a toggle on rollover frequency of 512Hz.

Any deviation from this value would be caused by an error in the xtal circuit.

Another way to confirm this independantly would be to write a toggle programme in assembler that uses a known number of cycles to toggle an output pin. I f the error here ties in with the TIM result fix the oscillator!

This is probably the closest you can get to actually measuring the ICG output.

Regards

David

[Geezer]

Hiya, David-

Thanks for the good suggestion re: measuring the ICG without the timer involved; I'll give it a whirl tomorrow.

There is legitimate focus being put on the XTAL circuit itself. However... Measuring its frequency directly tells us it is pretty darned good, within 40-50 ppm. The RTI, driven directly from it, bears this out. Just to rule it out completely I may inject a precision clock into EXTAL, but my gut tells me I won't see any difference: the RTI will be perfect, the PLL will be "off". Mercifully I've been wrong before.

Al