I have noticed that in the flash configuration file for the 56F8322 I am using, the flash controller clock divisor value is set to 0x0A and this seems to be an error. The proper value for the register is dependant on the SIM clock, and is calculated with the procedure described in section 22.214.171.124 of the Peripheral User Manual. For a system clock of 60MHz (the default system clock for the 56F8322) the proper register value would be 0x52 to produce a 197kHz flash programming clock.
Why is there a discrepancy between the flash clock divisor in the Peripheral User Manual and the 568322_flash.cfg file? If the clock divisor is dependant on the system clock, how can the flash_over_jtag programmer assume a clock divisor value without risking incomplete programming or damaging the flash?