ColdFire MCF54xx extemely slow system SRAM speed

[Rik]

Hello.

It seems that the MCF5485 system SRAM and MBAR (none cached area of course) have extrememly slow access time.

When I read sys SRAM it takes 20 (!!!) core clock cycles, when I write 16. I know the XL bus runs at half the core freq, so I expect 2 core clock cycle access time. If the sys SRAM is so slow, it's virtually useless !!!

Reading the PSC2 status reg (MBAR + 0x8804) takes 22 core cycles, reading the PSC2 recv buffer (MBAR + 0x880C) takes 24.

(By the way, PSC0 and PSC2 recv buffer takes 24 but PSC1 and PSC3 takes 22 cycles !?!?!?!?!?, writing to trans buffer (same addr) is always 18 cycles).

I tested this with code (a series of move.l  (a0),d0 with a slice timer around it to measure, a0 was set up earlier and no ints on of course) running from core SRAM1 set up for instruction space.

What's going on???

If I access (with the same code) core SRAM0 set up for data space I get single cycle access like expected.

If I run the same code accessing SDRAM with cache on, I get 50 cycles the first time (getting the cache line) and then 1 cycle, as expected.

Thanks for shedding any light on this.

Rik.

[salocin]

Hello Rik,

I just want to tell you that I have exactly the same problems. I performed several test on my board and I get the same results as you. MBAR and SRAM are extremely slow.

Did you find something ?

What are your external clock frequency and PLL settings?

Nico

[mnorman]

CPU accesses to the System SRAM and peripheral memory mapped registers takes several clocks due to the interface gaskets between the ColdFire bus and the XLB.  This is the expected behavior.  ColdFire accesses to the two local SRAMs and the cache occur in a single cycle.  The DMA and SEC are able to access the System SRAM quicker than the CPU due to the nature of their bus interface.

-mnorman

[salocin]

Hello,

thanks for the informations.

I'm really frustated to see that a 200MHz processor with a 100MHz bus frequency is quite unable to manage interrupts in less than 1 uS if you have to access a few peripherals registers (for example interrupt register, peripheral registers)!!!

It takes less time to access an external device connected to the flexbus than accessing the internal peripheral registers and I don't speak of the system SRAM .....

Moreover, I can't see in the datasheet a sentence clearly explaining or describing this limitation !!

[Vincent_2007]

Hello,

I am looking for a coldfire microprocessor for an application that require high performance.
The first benchmarks I tried on a MCF5485 evaluation board are not satisfying probably because of the problem you are talking about.
Can someone tell me if this problem is present on all the V4 coldfire core or only 547x and 548x ?
If the answer is positive, any advice for another processor I can choose ?

Thanks for your help,

Kind regards.
Vincent.

[salocin]

Hi Vincent,

I'm not sure whether the problems are relevant to the V4 core or not but it seems.
As long as you do not need to access registers outside the core it is ok.
Perhaps can you take a look at the MCF52xxx or MCF53xxx ?
What are your requirements ??

Regards
Nicolas