Rik van der Brugghen

ColdFire MCF54xx extemely slow system SRAM speed

Discussion created by Rik van der Brugghen on Oct 18, 2006
Latest reply on May 18, 2007 by nicolas colombain
It seems that the MCF5485 system SRAM and MBAR (none cached area of course) have extrememly slow access time.
When I read sys SRAM it takes 20 (!!!) core clock cycles, when I write 16. I know the XL bus runs at half the core freq, so I expect 2 core clock cycle access time. If the sys SRAM is so slow, it's virtually useless !!!
Reading the PSC2 status reg (MBAR + 0x8804) takes 22 core cycles, reading the PSC2 recv buffer (MBAR + 0x880C) takes 24.
(By the way, PSC0 and PSC2 recv buffer takes 24 but PSC1 and PSC3 takes 22 cycles !?!?!?!?!?, writing to trans buffer (same addr) is always 18 cycles).
I tested this with code (a series of move.l  (a0),d0 with a slice timer around it to measure, a0 was set up earlier and no ints on of course) running from core SRAM1 set up for instruction space.
What's going on???
If I access (with the same code) core SRAM0 set up for data space I get single cycle access like expected.
If I run the same code accessing SDRAM with cache on, I get 50 cycles the first time (getting the cache line) and then 1 cycle, as expected.
Thanks for shedding any light on this.