Mark Butcher

Instruction CACHE in the M5223X.....(?)

Discussion created by Mark Butcher on Oct 17, 2006
Latest reply on Jan 4, 2007 by Mark Butcher

Hi All


Perhaps some one can clear up a point....


Has the M5223X family instruction CACHE?


There is a register which is normally set up by using
| MCF5XXX_CACR_CLNF_00); // enable instruction cache


But is there actually an intsruction CACHE in the device?


In the manual there are details about this register but no details about the CACHE.


Comparing with the 5282 - in its manual it has the same details about the register PLUS a chapter dedicated to the CACHE.


My understanding is that the register is always there but not always with the CACHE support behind it. This means that tight loops will run faster on the 5282 that the M5223X (which is the present impression). But is this absolutely correct? Perhaps the CACHE chapter is missing in the manual and really there on the chip...(?).


Who can say with authority what is correct?


Another related question.


If I let some code run in SRAM will it actually run faster that directly from FLASH? This is typically the case for other processor families I have used but will I be wasting time trying because SRAM and FLASH code accesses are at the same speed??


And finally...we all know that we can let the M5223X devices run rather faster than the maximum specified 60MHz. But the problem is that no one wants to risk it in real-life because it is 'not-specified'. I wonder whether it may be of interest to have some form of 'official' specification for operating at limits (eg. to what temperate is it 'guarantied', what other restrictions must be observed to have 'guarantied' reliability, etc.) Otherwise it seems to be wasting a rather useful feature of the devices. It works but no one is prepared to risk anything - meaning that it is of no actual use to anyone. Just an idea!!


Best regards


Mark Butcher /