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SDRAM configuration help

Question asked by Adam Crowder on Oct 11, 2006
Latest reply on Oct 27, 2006 by Adam Crowder
Does anyone have a reference that describes in general how to configure the SDRAM controller in MCF5270 or the like?
 
All my experience to this point was with SRAM, imagine my surprise when I spent a DAY writing the SDRAM configuration, and an HOUR on the UART.
 
But anyway, now I've discovered that I've got it wrong somehow.  It works fine but using movem to READ the SDRAM fails in strange ways, I assume having to do with the speed at which that instruction fetches information from the RAM. 
 
Ideally, I'd like to find a document that discusses the configuration in general terms.  But if someone can give me a hint, that'd be cool too (tho I hope to have it solved by then
 
I have two Micron MT48LC4M16A2P-75:G chips to make a 32-bit memory, 16MB.  I can read and write individual addresses with this config but only get into trouble with movem (and, I suspect I'll be in trouble when I enable the cache..?)
 
My initialization function follows:
 
#define REFRESH_FREQUENCY 64000
#define BUSCLKS_PER_REFRESH (SYSTEM_CLOCK/REFRESH_FREQUENCY)     
#define REFRESH_COUNT (( BUSCLKS_PER_REFRESH / 16) - 1)
#if (REFRESH_COUNT > 0x1ff)
 #error "Refresh Count value calculated is out of bounds."
#endif
 MCF_SDRAMC_DCR   =
                    MCF_SDRAMC_DCR_RC(REFRESH_COUNT) +
                    MCF_SDRAMC_DCR_RTIM(1)        + // 6 clocks (65ns = 5.75 bus clocks)
//                     MCF_SDRAMC_DCR_IS             + Self Refresh is for low-power (sleep) mode
//                     MCF_SDRAMC_DCR_COC            + CKE = Clock enable (normal)
//                     MCF_SDRAMC_DCR_NAM            + We want controller to mux
                    0;
                    
 MCF_SDRAMC_DACR0 =
//                     MCF_SDRAMC_DACRn_IP              + Initiate Precharge All (later)
                    MCF_SDRAMC_DACRn_PS(0)           + // 32-bit port size
//                     MCF_SDRAMC_DACRn_MRS             +
                    MCF_SDRAMC_DACRn_CBM(4)          + // Based on BA0, 1 tied to A22, 23  p.18-8
                    MCF_SDRAMC_DACRn_CASL(2)         + // *** Not positive I've got this right
//                     MCF_SDRAMC_DACRn_RE              +
                    MCF_SDRAMC_DACRn_BA((long)SDRAM)  +
                    0;
 MCF_SDRAMC_DMR0 =
//                     MCF_SDRAMC_DMRn_WP            +
                    MCF_SDRAMC_DMRn_BAM_16M       + // 16MB of RAM
                    MCF_SDRAMC_DMRn_V             +
                    0;
 /*
 Init sequence for SDRAM (p. 18-19):
  1. Wait 100us with SDRAM lines idle.  Maybe this was done.
   2. Configure DCR, DACR, DMR (done, above.)
   3. Issue PALL command, read SDRAM Location, wait Trp. */
 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACRn_IP;
 *((long *)SDRAM) = 0;  // Longword Write to first bit of SDRAM
 __asm( "nop");
 __asm( "nop");
//  4. Enable refresh (DACR[RE]) and wait for at least 8 refreshes to occur
 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACRn_RE;
 Wait( 64 * 9);
//  5. Check DMR mask bits to make sure you can issue MRS command; change if necessary
   // Big RAM, looks OK
//  6. Issue MRS command: Set DACR[IMRS] then access location in SDRAM (address is the command)
/*  Micron SDRAM command binary: 00 0 00 010 0 000  
                                 | |  |   | |   +-Burst length = 1
                                 | |  |   | +-----Burst type sequential
                                 | |  |   +-------CAS latency = 2 (3 also supported)
                                 | |  +-----------Standard Operation
                                 | +--------------Programmed Burst Length
                                 +----------------Reserved
   That's all 0's except for A5.  RAM A5 connects to CPU A10 (schematic),
   so access SDRAM + 0x400 to send this command.
   *** This command may NOT be valid for the other sources for SDRAM.
 */
 MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACRn_IMRS;
 *((long *)(SDRAM + 0x400)) = ~0;  // should hit both of them
    
At the end of configuration, the registers contain:
DCR0A = 0x0253
DACR0A = 0x1000A400
DMR0A = 0x00FC0001
 

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