undocumented ECT difference from HC12 to S12

[imajeff]

I am converting a project
from XC68HC912BC32 (discontinued)
to MC9S12DG128.

At first I could not see why the output OC1 was not pulsing. This output compare software did work in the BC32 and the addresses were adjusted for DG128.

It turns out that when I read port T (PTT) while the output compare pin logic is enabled, it doesn't show the OC1 level. I relied on this in the BC32 to track whether the next step was to raise or lower the pin. When using DG128, this always reads zero even when the pin was high from timer event OC1 with TCTL2 = 0x0c (I suppose PTT just reads the last value from a write to PTT).

The way to convert my project as directly as possible was to read PTIT instead. Since PTIT reads actual input level of the pin, it could also detect wiring errors. At least I like that idea.

My suggestion is that the documentation should be updated to indicate that reading PTT reads only the GPIO output level, not the output compare levels as one would be accustomed comming from older ECT version(s).

[Alban]

Dear Imajeff,

May you please check one thing ?

S12DG128 Port T is shared between a TIMER and I/O.

I imagined that in S12 like on others, the Data Direction Register (DDRT) would decide what a Read is: either the level of the pin or the content of the data register (PTx).

Alban.

[imajeff]

Alban, Thank you for bringing up the DDRT even though I might have misunderstood why you were suggesting it.

I realize that your suggestion to change the DDRT bit was worth trying, even though it doesn't make sense, is not documented, and I didn't think I had changed the DDR bit since the BC32 design. So I went back to the bench and tried it.

Sure enough, I found that I have set it as output. To my amusement, setting DDR to input began showing the actual driven level in TC as I had expected before. Of course OC1 forces the pin as output so it would still not read actual pin level. Also I found that when DDR was set output, writing to TC did not change what was read from TC (always zero).

I suppose that this means the combination of enabling OC1 output pin (TIOS/TCTL2) and setting DDR as input actually means "enable reading the OC output buffer level instead of reading nothing". Well, that is most certainly not documented, so thank you for suggesting it.

My question now is, does this work the same way in 68HC912B32 ? I don't have that setup now so I can't test it easily. If I were to change the DDR as output would it stop working also?

[imajeff]

The function of ECT I use is quite similar on the two devices (68HC912BC32 and 9S12DG128B). Yes, both devices multiplex (share) the pin between OC (output compare) and GPIO, so that is not the difference between the two. Maybe you are thinking I'm trying to use the pin as GP input, but no, it is an OC output and no other function.

Two different things:

1. If I were using as GPIO output, then I can read the bit in PT to see if it is currently driving the pin high or low. This apparently works same in both, But I am not using as GPIO.
   
2. I enabled the OC to drive the pin. I was merely reading PT to see if OC1 was currently driving the pin high or low. This works in the BC32, but not in the DG128. My point is that I see no documentation of the difference.

For the most part I am posting this for others to supplement the docs. I suppose I'll try suggesting to Freescale that they add it to the docs, but it's been frustrating in the past, you know.

[Alban]

Hello,

That is where I got my feeling confirmed.

In S12DTB128PIMV2.pdf p°21:

PTT: If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read.

PTIT: This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins.

DDRT: This register configures each port T pin as either input or output. The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In these cases the data direction bits will not change.

The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled.

The timer input capture always monitors the state of the pin.

DDRT[7:0] — Data Direction Port T
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.

Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTT or PTIT registers, when changing the DDRT register.

Cheers,
Alban.

[Steve]

As Alban says this functionality is generally true. Another example is that the output level on a PWM signal can be read from Port P. If Port P has a keyboard interrupt function then you can use this to detect the mark point or period point of a PWM as well (and generate an interrupt if required).