Working with the Code Warrior for the MCF52235 I find errors on the header file GPIO.H.
I listed this errors in another Thread but I have no reply in last 2 days. Is there someone in FREESCALE that is working on this bugs? It isn't my job but I hve to check or rewrite myself all headers file to start working better with this micro?
My check is complete on gpio.h file, I have only some question before attached in this thread:
In some ports we have up to 4 functionality for each pin, as described in Table 2-1 of the Reference Manual. In the bit definition for this register (PxxPAR) there are no mention on some of them. one example is:
/* Bit definitions and macros for MCF_GPIO_PNQPAR */#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2)#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x0003)<<4)#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6)#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x0003)<<8)#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10)#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x0003)<<12)#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14)#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000)#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004)#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010)#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040)#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100)#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400)#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000)#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008)#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C)
Note that the last 2 rows are corrected because were wrong (were 0x8000 and 0xC000).
In table 2-1 I read that it could be respectively:
PRIMARY SECONDARY TERTIARY QUATERNARY
IRQ2 --- FEC_RXD PNQ
IRQ3 --- FEC_RXD PNQ
IRQ5 --- FEC_RXD PNQ
IRQ6 --- FEC_RXER PNQ
My question is: where are the Tertiary function definition for pins 2, 3, 5, and 6 ?
Note that this is also true for other QUAD FUNCTION PIN ASSIGNMENT REGISTER.