Richard Serge

Slo-Mo Debug with slow clock

Discussion created by Richard Serge on Sep 1, 2006
Latest reply on May 14, 2007 by Tom Monroe
The layout: Codewarrior 5.1, assembly, P&E debugger with QG8 demo board.

I'm trying to use the internal reference clock (in FBILP mode) for the chip's clock. I need low power and don't need speed. The data sheet says that in this mode the ICSLCLK (from the FLL) is disabled and therefore cannot be used for the BDM clock. So it uses the BUSCLK, which is really slow. Screen updates in the debugger take forever. OK, I understand that.

So, until I get mu code debugged I try using FBI mode. Says that in this mode the FLL is enabled and the ICSLCLK will be used to drive the BDM. I expected to see a full-speed debugging session in this mode, but I don't. It's the same when in FBILP.

What do I need to do to get a slow BUSCLK for my app and a fast clock for the BDM?

In FBILP mode I have:
ICSC1 = %01000110 (Int ref clock selected, IREFS=1, IRCLKEN=1)
ICSC2 = %00001000 (Bus Freq /1, LP = 1)

In FBI mode I have:
ICSC1 = %01000110 (Int ref clock selected, IREFS=1, IRCLKEN=1)
ICSC2 = %00000000 (Bus Freq /1, LP = 0)

Also, in both modes SOPT1 = %11010010 (COP on, debug pin enabled, reset disabled)

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Second Question: What exactly is the function of ICSIRCLK (enabled by IRCLKEN)? The data sheet describes how the signal is generated, but not where or how it is used (search the data sheet pdf for ICSIRCLK).

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Third Question: In ICSCS2 it says for the LP bit when set, "1 FLL is disabled in bypass modes unless BDM is active". This would lead me to believe that, contrary to what it says (10.4.1.4) about the FLL not being available for BDM, that the FLL is available when debugging when LP is 1. And if the FLL is available for the BDM clock, shouldn't that make for a normal speed debugging session even when LP is a 1? Can anyone clear this up for me?

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