Mark Butcher

QSPI - offset after reset?

Discussion created by Mark Butcher on Aug 21, 2006
Latest reply on Aug 31, 2006 by Mark Butcher
Hi All
Who has more experience with the QSPI and can explain the following?
I have an MC5213 and am using the QSPI to read in inputs via a shift register chain.
I initialise the QSPI for 10MHz master mode and read in one byte of 8 bits when starting to get some ID bits at the start of the shift register chain.
After that the shift register chain is read periodically by performing 2 x 13 bit reads.
This works fine.
Now I reset the board (not powerup, but by asserting RSTI). Using a logic analyser I see that the operation is identical and the data being received from the shift register chain is identical. However the data in the QSPI buffers is shiften by about 4 or 5 bits - and not always the same shift (therefore can also not be compensated).
So summerising:
After a power on reset it works perfectly every time. On a RSTI reset the data is shifted in the QSPI registers. Don't forget the data CS, CLK, DIN are identical, confirmed using logic analyser.
So what's going on? All data bits are there but offset...and why only after a reset but not power on. It is as if the RSTI is not performing the same reset as when removing power.
By the way. If I remove the initial 8 bit transfer performed once after startup the problem doesn't occur ()as far as I can remember), indicating that the offset may have something to do with moving from 8 bit to 13 bit buffer mode but it is also not totally stable.
So what is the reason???
Mark Butcher