Andy Neathway

PIT timer running too slow

Discussion created by Andy Neathway on Feb 23, 2012
Latest reply on Feb 29, 2012 by Andy Neathway

I have setup my clocks on K60 tower to be 96Mhz core, 48Mhz bus, and 24Mhz flash.....

However the fastest I can get PIT interrupt is 3Khz! with a reload of 1...

Can someone check this for me..... anything else needs setting up?

 

PIT setup:

void PIT_init(void) {
    SIM_SCGC6 |= (1 << SIM_SCGC6_PIT_SHIFT);     // enable clock gate to PIT
    PIT_MCR = 0;                                // PIT enable
    PIT_TCTRL0 = 0;                             // clear control register
    PIT_TFLG0 = 1;                                // clear IRQ flag
    PIT_LDVAL0 = 0x00000001;
    PIT_TCTRL0 = 2;                             // enable PIT0 interrupts
    PIT_TCTRL0 |= 1;                            // start PIT0
    NVICIP68 = 0x00;
    NVICICPR2 = 1 << ((68)%32);
    NVICISER2 = 1 << ((68)%32);
}

 

Clock setup:

      /* Switch to FBE Mode */
      /* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0, */
      OSC_CR = (uint8_t)0x00u;
      /* SIM_SOPT2: MCGCLKSEL=0 TRACECLKSEL=1 */
      SIM_SOPT2 = SIM_SOPT2_TRACECLKSEL_MASK;
      /* MCG_C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
      MCG_C2 = (uint8_t)0x24u;
      /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
      MCG_C1 = (uint8_t)0x9Au;
      /* MCG_C4: DMX32=0,DRST_DRS=0 */
      MCG_C4 &= (uint8_t)~(uint8_t)0xE0u;
      /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=25(50MHz / 25 = 2MHz)*/
      MCG_C5 = (uint8_t)0x18u;
      /* MCG_C5: PLLCLKEN=1 */
      MCG_C5 |= (uint8_t)0x40u;            /* Enable the PLL */
      /* MCG_C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
      MCG_C6 = (uint8_t)0x00u;
      while((MCG_S & MCG_S_OSCINIT_MASK) == 0u) {
    /* Check that the oscillator is running */
      }
      while((MCG_S & MCG_S_IREFST_MASK) != 0u) {
    /* Check that the source of the FLL reference clock is the external reference clock. */
      }
      while((MCG_S & 0x0Cu) != 0x08u) {    
    /* Wait until external reference clock is selected as MCG output */
      }

     //FBE_PBE

       /* Switch to PBE Mode */
      /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
      MCG_C1 = (uint8_t)0x82u;
      /* MCG_C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
      MCG_C6 = (uint8_t)0x40u;

     //PBE_FEI

      /* Switch to PEE Mode */
      /* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
       MCG_C1 = (uint8_t)0x02u;
      /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=25 */
      MCG_C5 = (uint8_t)0x18u;
        
      
      SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(3));
      /* MCG_C6: LOLIE=0,PLLS=1,CME=0,VDIV=50 (2MHz * 48 = 96MHz) */
            MCG_C6 = (uint8_t)0x58u;
      while((MCG_S & 0x0Cu) != 0x0Cu) {    
    /* Wait until output of the PLL is selected */
      }
      while((MCG_S & MCG_S_LOCK_MASK) == 0u) {
    /* Wait until locked */
      }
      /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=1 */

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