Mariusz Bernacki

HCS12 problem with address latching during write cycle

Discussion created by Mariusz Bernacki on Jun 16, 2006
Latest reply on Jun 26, 2006 by Jeff Smith
Hello All,
 
I'm using MC9S12DT256 microcontroller device configured with access to external RAM memory. And I have a big problem with address latching from multiplexed address-data bus during write cycle. I'm using 74AC573 latch with standard configuration to latch address by negative edge of ECLK signal (there is inverter AC04 beetween ECLK uC pin and AC573 latch in order to negate ECLK signal). During read cycle from external memory this works fine but while making a write cycle the latch AC573 doesn't catch the address and latches the data. It seems that address vanishes to fast compared to ECLK edge and inverter makes additional delay - all these things cause that AC573 can't latch valid address. How can I fix this?
 
Does anybody have similar problems? I need an urgent help with this case!!! What can I do to fix this problem! Please HELP me!!!

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