Enabling data cache affects ability to see register value changes?

[DavidHearn]

I've got some code which has setup the 5 DSPI pins on the ITX-Header connector of a M5475EVB for GPIO.

We're trying to sample the values of these pins as fast as possible and appear to have solved a number of issues we had with the performance, one of the ways was to enable data, branch and instruction caches.

However, now we've got something to drive the pins, I found that when we read the MCF_GPIO_PPDSDR_DSPI register, we get the same value back each time. The value may change between board resets, but appears constant during execution, even when we're altering the states of the pins externally to known states.

After a comparison with an older version which worked, I tracked it down to the data cache. It seems that by setting the Enable Data Cache (DEC) bit in the CACR causes the processor to cache the value of the register, and never read it again, even though it's being changed (though probably not to the processor's/cache's knowledge).

Any advice about how to overcome this?

Thanks

[DavidS]

Hi David,

Look at the MCF5475 Cache Operation section 7.9.1.2.

I think you need to cache inhibit the memory mapped register space using an ACR register.....or alternatively cache inhibit all memory map with CACR and use ACR's to define cacheable space.

Regards, DavidS

PS

Thank you for posting your solutions to issues!

[DavidHearn]

Okay - after giving up for a while to mask out the MBAR region from the data cache (I couldn't get it to work), I retried it a month or so ago and was successful.

What I used was, in asm_startmeup in mcf548x_lo.s

/* Set the ACR0 to disable cache for MBAR + System SRAM (0x10000000 to 0x100FFFFF) */
move.l #0x1000C040,D0
movec D0,ACR0

/* Invalidate the data, instruction, and branch caches */
move.l #0x810C8100,D0 /* Enable data, brach and instruction caches - cannot do with without excluding MBAR section */
movec D0,CACR


I've no idea if I've masked out too large an idea - all I can say it is works for me. It showed a performance increase over just enabling the branch and instruction caches. Without setting the ACR0 value, enabling the data cache would result in reading registers to return the same value.

Hope that's helpful

David