David Hearn

Enabling data cache affects ability to see register value changes?

Discussion created by David Hearn on Jun 15, 2006
Latest reply on Jan 17, 2007 by David Hearn
I've got some code which has setup the 5 DSPI pins on the ITX-Header connector of a M5475EVB for GPIO.

We're trying to sample the values of these pins as fast as possible and appear to have solved a number of issues we had with the performance, one of the ways was to enable data, branch and instruction caches.

However, now we've got something to drive the pins, I found that when we read the MCF_GPIO_PPDSDR_DSPI register, we get the same value back each time. The value may change between board resets, but appears constant during execution, even when we're altering the states of the pins externally to known states.

After a comparison with an older version which worked, I tracked it down to the data cache. It seems that by setting the Enable Data Cache (DEC) bit in the CACR causes the processor to cache the value of the register, and never read it again, even though it's being changed (though probably not to the processor's/cache's knowledge).

Any advice about how to overcome this?