I am wondering about the difference between starting the M5213 (and similar) Coldfire processors with an external 8 MHz crystal and CLKMOD0/1 = 10 and 11.
With '10' the crystal is selected with PLL disabled and with '11' the crystal is selected with PLL enabled.
When PLL is selected is it correct that it will multiply the crystal frequency by x6 (8 x 6 = 48MHz). I figure out x6 due to default register setting.
Does the chip then automatically wait until the PLL has locked to this frequncy before continuing with the reset sequence?
Does and one know the details and know when the PLL enable option would not be advisable?