Mark Butcher

PLL in M52235

Discussion created by Mark Butcher on May 6, 2006
Latest reply on Sep 1, 2006 by Mark Butcher
I am rather confused about the PLL in the M52235.
Accoring to the documentation, the 25MHz cyrystal frequency should first be divided to within the range 1..10 MHz. This is done by programming MCF_CLOCK_CCHR. Then the frequency is multiplied by 12 to get the maximum frequency of 60MHz.
My findings have been that it doesn't react to CCHR settings. It seems as though there is a fixed divide by 5 in the input because the *12 really does give 60MHz.
Looking at example code in the CodeWarrior project delivered with the EVB I see that the CCHR setting is commented out - also according to the documentation a value of 4 and not 5 in the register would give the /5 (?). Here is the code from CodeWarrior files:
//MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 25MHz / 5 = 5MHz
 /* The PLL pre-divider affects this!!!
 * Multiply 25Mhz reference crystal /CCHR by 12 to acheive system clock of 60Mhz
Then the last thing that I see is that the PLL locks but the value in SYNSR is 0x38. The SR in the documentation has bit b00100000 always as zero so this should not be able to happen.
Is the design of the PLL really different in the M52235? Has the (preliminary) documentation not yet been adapted?
Any ideas?
Mark Butcher