Regarding MC9S12NE64 INITRM REGISTER

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Regarding MC9S12NE64 INITRM REGISTER

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rammohank
Contributor I
Hai frnds,

I was not able to understand the RAMHAL BIT present in INITRM REGISTER.
Will u please help me by giving some example.

Ram Mohan K
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mjbcswitzerland
Specialist V
Hi
Most RAM setups on the NE64 use the initialisation 0x39  (note that this can only be written once in normal mode).
This sets the internal RAM position to b0011100000000000 and aligns it to the top of the mappable space.
The RAM position block is 0x3800..0x3fff (the next possible position is 0x4000).
Now the SRAM size in the NE64 is 8k (0x2000).
Because the RAMHAL bit is set, the block ends at the top of the range (0x3fff).
Since the SRAM is 8k in size, it thus begins at 0x2000.
0x39 thus configures the SRAM to be addressable between 0x2000 and 0x3fff.
 
If the RAMHAL were not to be set (value 0x38) then it would mean that the RAM is aligned to the bottom of the block (in our case 0x3800). Since it is 8k in size, it would be addressable from 0x3800..0x57ff.
 
A value of 0x20 would in fact position the SRAM in the NE64 to the same position as 0x39, it specifies the lower address position rather than the higher address position but produces the same result. [I never tested this but it is probably the case]
 
[Since the only really practical setup of the SRAM in the NE64 from 0x2000..0x3fff then it is best to do the same as every one else and just set 0x39 on inialisation...]
 
Regards
Mark Butcher
www.mjbc.ch
 
 
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EMontanez
NXP Employee
NXP Employee
Mark,

Thanks for always helping on the HCS12 forums. On this one, I have to slightly correct you. INITRM is a very peculiar register. One that I just recently had to perform a deep dive to better understand its functionality. I have summarized it below:

INITRM functionality is dependent on the RAM size on your device, in this case it is 8K for the NE64.

Below are the RAM bits in the INITRM register that are valid for relocating the ram dependent on your RAM size:

2K -> RAM15:11 -> 5 bits are valid
4K -> RAM15:12 -> 4 bits are valid
6K &
8K -> RAM15:13 -> 3 bits are valid
10K &
12K &
14K &
16K -> RAM15:14 -> 2 bits are valid

Let me explain how I derived this using the 8K RAM example on the NE64. A 8K RAM block is equivalent to 8192 bytes, which is an addressable range of $0000 - $1FFF. To relocate RAM in $1FFF chunks the binary equivalent is 0b XXX1 1111 1111 1111. Therefore, the top 3 bits are the only ones that can be changed in INITRM to move in $1FFF chunks.

Now on to the RAMHAL bit. This bit only applies to RAM sizes that are non-powers of 2. These are 6K, 10K, 12K, and 14K. In these cases if the RAMHAL bit is set the RAM starts at the top of the memory map ($FFFF) and works downwards, determined by the RAM bits in INITRM.

For those RAM sizes which are powers of 2: 2K, 4K, 8K, 16K..... RAMHAL is ignored. Therefore, the NE64 ignores RAMHAL and writing 0x39 or 0x38 to INITRM does not make a difference. I hope this clears things up.

:smileyhappy:
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imajeff
Contributor III
I found it important to look at the memory map in the device user guide. for NE64, see Figure 1-2, User configurable Memory Map. Notice the RAM says "Mappable to any 8k boundary" This "mappable" block is the only one that determines the use of INITRM.

I was originally real confused while trying to help someone with an older device because it is not always mappable to the same space as size of memory. For example, my MC68HC912BC32 is 1K RAM, mappable to 2K space.

Message Edited by imajeff on 05-10-200611:09 AM

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mjbcswitzerland
Specialist V
Hi Moderator
Yes you caught me out a bit in that one - I originally though that the bit really had no use but then was not so sure and I had a bit of an educated guess at exactly how it works.
Since the register can only be written once and this is performed by the serial monitor in the DEMO9S12NE64, it is actually not possible to tests it without a BDM (which I didn't have handy at the time).
My "educated" quess was not exactly correct but I thought it would be better to present an explanation to get the ball rolling.
Regards
Mark
 
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EMontanez
NXP Employee
NXP Employee
Mark,

Well that's exactly what the forums are for! If we all were afraid to take educated guesses, this forum would be mute.

Plus, it helps me keep the rust off. I found an engineering bulletin that addresses the INITRM subject.

See http://www.freescale.com/files/microcontrollers/doc/eng_bulletin/EB386.pdf?srch=1

By the way, my name is Ed. I should start posting it...to avoid the MR. MODERATOR cliche.
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mjbcswitzerland
Specialist V

Thanks Ed, I checked out the Engineering Bulletin which clears up the issue.

'Till the next time, regards

Mark

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rammohank
Contributor I
Hi Mark and Ed..

Thanks for the solution..
I gone thru the pdf link posted by Ed..
It is very helpful...
I gone thru so many pdfs, but there is no use ..
At last i solve my prob thru this forum..


Thanks and regards
Ram MOhan K
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