Are you using the /SS signal on the slave? I had the same problem when I had the /SS tied low. It worked after tying it to an enabled /SS from the Master.
Hope that helps,
Todd Morton
Do you have the CPOL and CPHA bits in the SPICR1 Register set to the same values in both Master & Slave device?
This can cause all sorts of wierd interactions!
Message Edited by MJB on 04-07-200604:58 PM
Hello MJB,
For the SPI to work when CPHA = 0, /SS line at the slave must go high again at the end of each byte transfer, and then return low for the next byte. This is not the case when CPHA = 1, where /SS may remain low. I suspect that, if you are trying to use /SS as an output at the master, to feed the /SS input at the slave, this may not be set up correctly. You could alternatively use a general purpose output to drive the slave /SS line.
Regards,
Mac
Message Edited by MJB on 04-10-200611:51 AM
Hello MJB,
MJB wrote:
Can I have CPHA=0 on the slave and not have the requirement of SS going high between byte transmissions?
Since your slave end is another MCU, this will require SS going high to receive the byte. I do not understand why you must have CPHA = 0 since you have control over the setup of both ends of the link. The principal requirement is that the master and slave must match for both CPHA and CPOL.
What I have and want to receive is a 32 bit stream which is indicated as valid by a negative active line. So the first positive edge clocks the data in and on the last negative edge the line which indicates whether the data is valid goes high.
To use the SPI, each group of 32 bits must be handled as four separate bytes, with sufficient time between the bytes to allow each received byte to be placed in a buffer, presumably by the SPI receive ISR. I am not clear about your handshake, and what you mean by a "negative active line" - do you refer to the SCK line? If you need to detect whether the received data contains errors, you could always return a suitable acknowledge byte to the other end in response to each 32 bits.
Regards,
Mac
Message Edited by MJB on 04-10-200602:10 PM
Hello MJB,
To further clarify the actual data transfer from the external source -
This will help determine what are the correct settings for CPHA and CPOL.
Whether the 32-bit transfer (handled as four bytes) can work or not will also depend on the incoming clock rate, and whether there is enough time to process the previous byte before the first clock edge of the following byte. So the SPI clock rate must be relatively slow - an indication of the SPI clock rate, and also your bus rate, would be useful.
Regards,
Mac
Message Edited by MJB on 04-12-200610:25 AM