Hi,
We've modified the EVK Switch demo to be sending direct data packets at full speed from a coordinator to an FFD device (RX on when idle). We only send one 102 byte packet at a time, waiting for a positive or negative acknoledgement before re-sending. This sends approximately 120 packets per second.
We're sending dummy data but we've added our own little simple 8 bit checksum inside the data packet. At reception on the device, we verify the checksum and enter a dead loop if it fails.
We've notice that the program will enter the dead loop after some varying amount of time (from 15 min, to a couple of hours). This would indicate that the received data was incorrect, but that the CRC of the MAC/PHY still accepted it.
Is this possible? Any ideas?
Marc