On-chip flash programming routines for QT/QY & AN1831 (Rev 3)

Discussion created by bigmac on Mar 26, 2006
Latest reply on Mar 28, 2006 by bigmac
This issue is really addressed to Freescale, but if others can throw light on the situation, I would welcome any comments.
I refer to Revision 3 of AN1831 (Nov 2005), and the programmming of flash for storage of non-volatile data within an application, for QT/QT devices specifically.  I make the following observations with the revised AN.
  1. The AN makes no differentiation between the older (classic) devices, and the newer (A-suffix) devices. In fact it makes no specific mention of the latter.
  2. It states that the "page erase" issue does not apply to QT/QY devices.  But when using the PRGRNGE routine, row boundaries must now not be crossed, for the QT/QY devices only.
  3. It is stated numerously that the QT/QY devices now only support 1 MHz bus frequency for erase or programming operations (with CPUSPD = 4).
If my observations are correct, this seems to be "shifting the goal posts" somewhat, from the previous situation.
I currently do use the ROM-based routines in a number of applications, for page erase and for programming of classic devices only.  I have been doing so (successfully) for the last two years or so, using the internal oscillator (bus clock = 3.2 MHz), and CPUSPD = 13.  So the following questions arise -
  • Do the new limitations apply to both classic and A-suffix devices?  If so, when did this take effect, and how do I recognize whether a batch of devices will have the new limitations, or not?  The mask set ID does not currently appear on any of the pieces within my stock (only a date code).
  • For my existing applications, do I need to modify my usage to reflect these changes (assuming continued use of the classic devices) - perhaps to implement my own routines?
  • Of particular concern is the lowering of the maximum bus rate to accommodate erase and programming.  Since the classic device does not have a 1 MHz bus option, does this imply that an external 4 MHz crystal/oscillator must now be used where flash programming within an application is required?  What would be the likely effect of continuing to use the 3.2 MHz bus rate (with CPUSPD = 13)?
Of course, if the additional limitations (and the Application Note) apply only to the new A-suffix devices, does there still remain a "page erase" issue for the classic devices (as there once was)?
Thank you in anticipation.