I've implemented a component using PDB, ADC and DMA.
PDB triggers ADC which triggers DMA which copies data to a buffer.
From time to time DMA is not enabled to copy the data, and so result register of ADC is still full with the previous result, when the PDB tries to trigger the ADC once again.
I don't want to give in details why DMA is not enabled from time to time, so try to take it for a fact.
The problem is when I try to clear the error in PDB status register, and cannot do it.
In datasheet it is told to write 1's to the error bits to clear them.
Doesn't matter what I write (1's or 0's), the bits are never cleared.
I haven't found anything in errata as well.
Thanks in advance,