Frank Zane

08lj12: SPI operate EEPROM (93c56)

Discussion created by Frank Zane on Mar 17, 2006
Latest reply on Mar 27, 2006 by Frank Zane
the EEPROM chip is 93c56. when operate EEPROM thr SPI, all 93c56-PC(DIP, 2MHz clk) is ok. but 93c56-SI27(SOT, 1MHz clk), all write is ok(this verified by other device), but when read, those result data is shift right one bit, just read out 7 bits of most significant byte.

since 93c56 is raising CLK shift in, and falling CLK shift out, and the SPI is all raising SPSCK shift in/out current bit. it seems some critical state when MISO data shift in. or the status just like SPSCK lost the last half edge(one falling edge) at end.

those SPI Baud Rate Select Bits already set to 1/128 of fbus. Power supply is enough.

so, any advice?