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HC908QT2, fix frequency generation but not working via TCH1

Question asked by xiaolaba on Jul 18, 2012
Latest reply on Jul 20, 2012 by xiaolaba

Hello,

we need help and advice to work out a soltuion

the basis of code snippet is off from AN2475 (use TIM to Generating a PWM Signal), slightly modification to the code of which is giving fix frequency output via PTA0 pin (TCH0),

however, we want to switch this off to PTA1 pin (TCH1) to became output. PTA0 is preserved for other purpose as board assembly has been done.

try with code following, setup to ouput for TSC1, but does not work.

 

thanks

 

xiaolaba

 

;* Program Timer Interface Module (TIM)
;* Initializing PWM

             mov    #initTim,TSC   ;Reset & Stop Counter
             mov    #$36,TSC   ;Reset & Stop Counter, Timer 1 - Cleared + Stopped, ; Clicks once every 64 BUS Cycles

             mov    #periodH,TMODH ;Set PWM period
             mov    #periodL,TMODL ;T = periodL*16 int. bus*(1/bus_clk)

;             mov    #InitpwmH,TCH0H
;             mov    #InitpwmL,TCH0L ;initial value for output compare (50%)
;             mov    #TSC0_setting,TSC0   ;enable buffered PWM in channel 0   ; PTA0/TCH0

             mov    #InitpwmH,TCH1H
             mov    #InitpwmL,TCH1L ;initial value for output compare (50%)
             mov    #TSC0_setting,TSC1   ;enable buffered PWM in channel 1   ; PTA1/TCH1
           

;start timer           
;             mov    #Timer_setting,TSC   ;Disable interruption, clk = internal bus / 16
;             mov    #1,TSC   ;Disable interruption, clk = internal bus / 2 = max 50KHZ
             mov    #0,TSC   ;Disable interruption, clk = internal bus / 1 = max 90KHZ

           


;strat ADC 3
; ADC test, working
             mov    #ADC_CLK_setting,ADICLK ;ADC clock, bus clock / 16
       
            bclr   PTA0,PTA    ;initialize PTA0 for serial comms
                               ;set to output, port pin see this 0, output is 0
                               ;change to input pin, default is pullup, output is 1

;PTA0, frequency output and timer setting
;             lda #20  ;76.9 KHZ
             lda #15  ;100.8 KHZ      
;             lda #10  ;147 KHZ
;             lda #5   ;268.8 KHZ
;             lda #2   ;537.6 KHZ
;             lda #1   ;806.4 KHZ
;             lda #0   ;DC, why ?     
             sta TMODL

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