HC908QT2, fix frequency generation but not working via TCH1

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HC908QT2, fix frequency generation but not working via TCH1

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xiaolaba
Contributor I

Hello,

we need help and advice to work out a soltuion

the basis of code snippet is off from AN2475 (use TIM to Generating a PWM Signal), slightly modification to the code of which is giving fix frequency output via PTA0 pin (TCH0),

however, we want to switch this off to PTA1 pin (TCH1) to became output. PTA0 is preserved for other purpose as board assembly has been done.

try with code following, setup to ouput for TSC1, but does not work.

 

thanks

 

xiaolaba

 

;* Program Timer Interface Module (TIM)
;* Initializing PWM

             mov    #initTim,TSC   ;Reset & Stop Counter
             mov    #$36,TSC   ;Reset & Stop Counter, Timer 1 - Cleared + Stopped, ; Clicks once every 64 BUS Cycles

             mov    #periodH,TMODH ;Set PWM period
             mov    #periodL,TMODL ;T = periodL*16 int. bus*(1/bus_clk)

;             mov    #InitpwmH,TCH0H
;             mov    #InitpwmL,TCH0L ;initial value for output compare (50%)
;             mov    #TSC0_setting,TSC0   ;enable buffered PWM in channel 0   ; PTA0/TCH0

             mov    #InitpwmH,TCH1H
             mov    #InitpwmL,TCH1L ;initial value for output compare (50%)
             mov    #TSC0_setting,TSC1   ;enable buffered PWM in channel 1   ; PTA1/TCH1
            

;start timer            
;             mov    #Timer_setting,TSC   ;Disable interruption, clk = internal bus / 16
;             mov    #1,TSC   ;Disable interruption, clk = internal bus / 2 = max 50KHZ
             mov    #0,TSC   ;Disable interruption, clk = internal bus / 1 = max 90KHZ

            


;strat ADC 3
; ADC test, working
             mov    #ADC_CLK_setting,ADICLK ;ADC clock, bus clock / 16
        
            bclr   PTA0,PTA    ;initialize PTA0 for serial comms
                               ;set to output, port pin see this 0, output is 0
                               ;change to input pin, default is pullup, output is 1

;PTA0, frequency output and timer setting
;             lda #20  ;76.9 KHZ
             lda #15  ;100.8 KHZ       
;             lda #10  ;147 KHZ
;             lda #5   ;268.8 KHZ
;             lda #2   ;537.6 KHZ
;             lda #1   ;806.4 KHZ
;             lda #0   ;DC, why ?      
             sta TMODL
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bigmac
Specialist III

Hello,

 

For unbuffered PWM operation on TIM channel 1, you will need the following channel initialisation -

    mov  #%00011010,TSC1  ; Clear Ch1 output on compare

 

If you require to change the TPM duty without any glitches, the channel compare interrupt will need to be temporarily enabled and the change to TCH1 done from within the ISR (when the output is already inactive).  Further channel interrupts should be disabled prior to exit from the ISR.

 

Regards,

Mac

 

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rocco
Senior Contributor II

Hi Xiaolaba,

 

I can't tell precisely, because I don't know what you have defined "initTim", "TSC0_setting" and "Timer_setting" as, but it appears from the comments in your code that you are trying to use buffered PWM. Buffered PWM will only output on channel 0.

 

If you need to output on channel 1, then you will have to use unbuffered PWM.

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xiaolaba
Contributor I

Hello Rocco,

thanks for reply. this is always excellent to learn something from others.

We are having a little follow up, and the code defination for my snippet.

If this has to uses unbuffered PWM, what could be done with tweaking to these code, and make it happen to TCH1. We have no debugging tool availabe at the moment, only boot loader programmer and the chips itself, and one hand held o'scope could be used to verify the output, these constraints hold up for a while until fix this issue.

 

initTim: equ    %00110000     ;Timer Status and control Reg. value;                ||||||||     TIM Status and Control Register;                |||||||+-PS0     - 0 Prescaler select bit;                ||||||+--PS1     - 0 Prescaler select bit;                |||||+---PS2     - 0 Tim clock source int. bus / 8;                ||||+----0       - 0;                |||+-----TRST    - 1 TIM reset bit;                ||+------TSTOP   - 1 TIM counter stopped;                |+-------TOIE    - 0 disable TIM overflow interrupts;                +--------TOF     - 0 TIM overflow flag bitTSC0_setting: equ    %00101010     ;TSC0 Initial Value;                ||||||||     TIM Channel Status and Control Register;                |||||||+-CH0MAX  - 0 Channel 0 Maximum Duty Cycle bit;                ||||||+--TOV0    - 1 Channel 0 toggle on overflow;                |||||+---ELS0A   - 0 |;                ||||+----ELS0B   - 1 |;                |||+-----MS0A    - 0 |;                ||+------MS0B    - 1 |-> Config TIM as buffered PWM;                |+-------CH0IE   - 0 disable Channel 0 CPU interrupt;                +--------CH0F    - 0 No input capture or output compareTimer_setting: equ     %00000100     ;Timer Register configuration value;                ||||||||     TIM Status and Control Register;                |||||||+-PS0     - 0 Prescaler select bit;                ||||||+--PS1     - 0 Prescaler select bit;                |||||+---PS2     - 1 Tim clock source int. bus / 16;                ||||+----0       - 0;                |||+-----TRST    - 0 TIM reset bit;                ||+------TSTOP   - 0 TIM counter active;                |+-------TOIE    - 0 disable TIM overflow interrupts;                +--------TOF     - 0 TIM overflow flag bit

 

 

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bigmac
Specialist III

Hello,

 

For unbuffered PWM operation on TIM channel 1, you will need the following channel initialisation -

    mov  #%00011010,TSC1  ; Clear Ch1 output on compare

 

If you require to change the TPM duty without any glitches, the channel compare interrupt will need to be temporarily enabled and the change to TCH1 done from within the ISR (when the output is already inactive).  Further channel interrupts should be disabled prior to exit from the ISR.

 

Regards,

Mac

 

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xiaolaba
Contributor I

hello Mac,
this is wonderful, it is working.

thanks

xiaolaba

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