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srio tx from cacheable memory

Question asked by Pavel Schukin on Jun 1, 2012
Latest reply on Jun 2, 2012 by jie yang


I use MSC8156ADS board and Spartan 6 connected to it by SRIO. Data transfers go by Ocean DMA succesfully only if memory blocks on MSC8156 is non-cacheable. But if the source address of ocnDMA transfer configuration is set for cacheable memory ocnDMA transmith zeros(digital loopback shows same result). I try to sweep cache for this memory but it is all the same. I see cacheable memory filled with true data while debugging, but ocnDMA transmits zeros.

How can i transmit by ocnDMA from cacheable memory? Thank you.