Mathieu Lafrance

DDR Drive strength and signal integrity with MCF54451

Discussion created by Mathieu Lafrance on May 14, 2012
Latest reply on May 15, 2012 by Mathieu Lafrance



We have a new design that is using MCF54451CVM180 alogside with DDR1 chip MT46V32M16P-6T from micron.


The clock is running at 80MHz, but the chip support up to 166MHz. It is a 2.5V DDR, not mobile.


The differential clock is terminated with a 100ohm resistor, and all other signals are terminated with 22ohm serie resistor. There is only one discrete chip, no DIMM, so it is a point to point application.


I've been fiddling around with termination and drive strength settings to find the best combination, since there is a little bit of over and undershoot on the signals. My guess is that signal was too strong, since the chip is alone and next to the CPU.


See attached file, REF1 in black is original setting, CH1 in blue is the same signal but with register FC0A_4074 set to 0x00 (Half strength 1.8V mobile DDR instead of 2.5V DDR1, as seen with CH1).


Signal quality is clearly better IMO, but the name of the register suggest this parameter should only be used with 1.8V mobile DDR. My understanding is that mobile DDR is usually point to point, this might explain the better signal quality.


Besides drive strength, what is the difference between those settings ?? :


00 Half strength 1.8V mobile DDR
01 Full strength 1.8V mobile DDR
10 1.8V DDR2 without on-chip termination
11 2.5V DDR1


Thanks for any help