DDR Drive strength and signal integrity with MCF54451

[Wipeout]

Hi,

We have a new design that is using MCF54451CVM180 alogside with DDR1 chip MT46V32M16P-6T from micron.

The clock is running at 80MHz, but the chip support up to 166MHz. It is a 2.5V DDR, not mobile.

The differential clock is terminated with a 100ohm resistor, and all other signals are terminated with 22ohm serie resistor. There is only one discrete chip, no DIMM, so it is a point to point application.

I've been fiddling around with termination and drive strength settings to find the best combination, since there is a little bit of over and undershoot on the signals. My guess is that signal was too strong, since the chip is alone and next to the CPU.

See attached file, REF1 in black is original setting, CH1 in blue is the same signal but with register FC0A_4074 set to 0x00 (Half strength 1.8V mobile DDR instead of 2.5V DDR1, as seen with CH1).

Signal quality is clearly better IMO, but the name of the register suggest this parameter should only be used with 1.8V mobile DDR. My understanding is that mobile DDR is usually point to point, this might explain the better signal quality.

Besides drive strength, what is the difference between those settings ?? :

00 Half strength 1.8V mobile DDR
01 Full strength 1.8V mobile DDR
10 1.8V DDR2 without on-chip termination
11 2.5V DDR1

Thanks for any help

[TomE]

> Besides drive strength, what is the difference between those settings ??

You didn't say what register you were looking at. I assume you mean:

16.3.6 SDRAM Mode Select Control Register (MSCR_SDRAM)

I had a similar problem with the MCF5329, detailed here:

https://community.freescale.com/message/66541#66541

The "single line response" from Freescale when I asked what the settings in a similar register to the one you're looking at was:

    "Read the IBIS file in the chip page downloadable from Freescale."

The IBIS file details a model for the I/O pins. There are different models listed for each mode, at least there were for the MCF5329 chip. I suggest you see if you can get the IBIS file for your chip.

You're checking the signals, but is the SDRAM working? This details how driving the SDRAM "too hard" (the chip default was "full strength") resulted in corrupted data.

https://community.freescale.com/message/66171#66171

Tom

[Wipeout]

Hi Tom,

Yes I meant MSCR_SDRAM.

Your posts are very helpful, thanks for sharing your findings.

Yes the DDR is working fine, we're going in EMI soon and I need to soften these signals to help pass the prescreen. Just wanted to know if I were going to break anything by using a settings labeled as "1.8V mobile DDR" for a non-mobile 2.5V DDR.

Seems like i'm not going to break anything :smileyhappy: