I'm reading the MCF5485 Reference manual 2.2.1.9, and 17.4.9 and I'm trying to understand the difference between /TA and a Data Strobe Acknowledge signal.
Is the cycle terminated as soon as /TA goes low?
Or is the data read and the cycle terminated on the rising edge of /TA?
Solved! Go to Solution.
> I'm trying to understand the difference between /TA and a Data Strobe Acknowledge signal.
There is nothing matching "Data Strobe Acknowledge" in the whole manual.
> Is the cycle terminated as soon as /TA goes low?
> Or is the data read and the cycle terminated on the rising edge of /TA?
The Reference manual doesn't give the details of this. You want the Data Sheet ("MCF5485EC.pdf") for this. The "8.1 FlexBus AC Timing Characteristics" section should tell you everything you want to know.
Tom
> I'm trying to understand the difference between /TA and a Data Strobe Acknowledge signal.
There is nothing matching "Data Strobe Acknowledge" in the whole manual.
> Is the cycle terminated as soon as /TA goes low?
> Or is the data read and the cycle terminated on the rising edge of /TA?
The Reference manual doesn't give the details of this. You want the Data Sheet ("MCF5485EC.pdf") for this. The "8.1 FlexBus AC Timing Characteristics" section should tell you everything you want to know.
Tom
As far as I can tell /TA (Transfer Acknowledge), /DSA (Data Strobe Acknowledge), and /DTAC (Data Transfer Acknowledge) are all the same and are used on the bus to acknowledge the transfer and terminate the cycle, at the end of the cycle.
Where as Intels /Wait asserts directly after chip select (I preausme to acknowledge the /CS) and de-asserts at the end of the cycle to acknowledge the data transfer.
If there are subtle differences between /TA, /DSA/ and /DTAC that are not obvious someone please enlighten me. Perhaps there is a reason for all the different names,,, or a story???
I have never worked with Intel hardware, so if I have /Wait wrong also someone please let me know.
Thanks