Dear freescale users,
glad to meet you. This is the first time I write here since I was using different silicon vendors untill now.
I started evaluating the MPC8313E board to test its PTP capablities (thanks to Alan Bartky for the great job he has done with the PTP stack and the freescale ethernet driver).
I am having toubles enabling the IEEE 1588 test pins (PPS, clock, ...).
I am using LTIB ltib-mpc8313erdb-20070824 (kernel 2.6.20). I have also
tried to use the latest LTIB, but had problems compiling the kernel
module bundled with the ptpdv2 since there have been a few changes in
the network api in the kernel 2.6.23. Anyway this is not a big problem.
From the documents it seems that the IEEE 1588 testpoints are shared
with the eTSEC1, so I am trying to change the mux settings to select the
test points via SICRL and SICRH registers.
Unfortunately when changing their value at run-time I get a system hang
(even the serial console is not responding anymore). I am not using
eTSEC1 (connected to the Vitesse switch) but just the eTSEC2 (connected
to the Marvell phy). I have also disabled eth0 with ifconfig eth0 down.
/home/marcoge # ./ptpv2d
Memory 0xe0000000 (size 0x00100000) mapped at address 0x30029000
IMMR = e0000000
SPRIDR = 80b00010
SICRL = 00000800
SICRH = 00000003
-> Here I change the value of SICRL and SICRH as follows:
// enable IEEE 1588 pins (disabling eTSEC1 phy)
*(IMMR + 0x114) = (*(IMMR + 0x114) & 0xCFFFFFFF) | 0x10000000;
*(IMMR + 0x118) = (*(IMMR + 0x114) & 0xF9FFFFFF) | 0x02000000;
and the system hangs.
I would also like to know how to interpret the 0bNN notation for pin n
Supposing I read that pin 28-29 are to be placed in configuration 0b01
which is the pin that goes to 1? 28 or 29?
I tried with both configurations to no avail.
I may be missing something.
Can you give me some suggestions on how to use these test pins?
I'll post here my discovering along the way.
Many thanks and best regards.