Richard DE MIRANDA

Choose Cycle Transmit Flexray Frame

Discussion created by Richard DE MIRANDA on Apr 26, 2012
Latest reply on May 10, 2012 by Richard DE MIRANDA

Hi,

 

I'm using an MCU 16-bit MC9S12XF512MLM. I have two Freescale developement tool card with the MCU. I would like to transmit an Flexray Frame in 2 or 3 different cycle :

 

I Explain, for example : I have a frame using slot ID 4, length 16, with data 0x00FF. I would like to send this frame just on the cycle 3 and 10.

 

You know that there is 64 communication cycle in the flexray protocol, and in my case i would like to send this frame on the same ID but in two different cycle.

 

Do you know how i can do that? Because with the freescale example which I use with my development tool card, i can't do it.

 

Here the définition of the configuration of an transmit frame :

 

const Fr_transmit_buffer_config_type Fr_tx_buffer_slot_01_cfg ={   1,                           // Transmit frame ID   242,                         // Header CRC   16,                          // Payload length   FR_DOUBLE_TRANSMIT_BUFFER,   // Transmit MB buffering   FR_STATE_TRANSMISSION_MODE,  // Transmission mode   FR_STREAMING_COMMIT_MODE,    // Transmission commit mode   FR_CHANNEL_AB,               // Transmit channels   FALSE,                       // Payload preamble   FALSE,                       // Transmit cycle counter filter enable   0,                           // Transmit cycle counter filter value   0,                           // Transmit cycle counter filter mask   TRUE,                        // Transmit MB interrupt enable   TRUE                         // FALSE - interrupt is enabled at commit side, TRUE - interrupt is enabled at transmit side};

 

And here, the function to tranmist a flexray frame :

Fr_tx_MB_status_type Fr_transmit_data(uint16 Fr_buffer_idx, const uint16 *Fr_data_ptr, uint8 Fr_data_length){    volatile uint16 * FR_DATA_FAR header_MB_ptr;        // Message buffer header pointer    volatile uint16 * FR_DATA_FAR Fr_CC_data_ptr;       // Reference to data array    volatile uint16 temp_value_1 = 0, temp_value_2 = 0; // Temporary variables used for bit operation    volatile uint16 Fr_MB_registers_offset_add_temp; // Temporary offset adress of message buffer registers    uint16 Fr_p;                                        // Temporary counter used for copying        // Temporary offset address of MB registers    Fr_MB_registers_offset_add_temp = Fr_buffer_idx * 4;    // Read the MB Configuration, Control and Status reg.    // Load MBCCSRn register and select only necessary bits    temp_value_1 = (Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] & 0xF900);    temp_value_1 |= FrMBCCSR_LCKT;              // Set Lock Trigger bit    Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;  // Lock MB        // Read the MB again for checking if the MB is locked    temp_value_2 = Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp];      if(temp_value_2 & FrMBCCSR_LCKS)            // Is the MB locked?    {                                           // Yes        // Clear Transmit Buffer Interrupt Flag            temp_value_2 &= 0xF900;                 // Select only necessary bits            temp_value_2 |= FrMBCCSR_MBIF;          // Set MBIF flag - clear TX MB interrupt flag         Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_2;  // Clear Transmit Buffer Interrupt Flag        // Load current MB index        Fr_buffer_idx = Fr_CC_reg_ptr[FrMBIDXR0 + Fr_MB_registers_offset_add_temp];        // Calculate the message buffer header         header_MB_ptr = ((volatile uint16 * FR_DATA_FAR)(Fr_HW_config_ptr->CC_FlexRay_memory_base_address) + Fr_buffer_idx * 5);                // Calculate MB Data pointer        Fr_CC_data_ptr = ((volatile uint16 * FR_DATA_FAR)(Fr_HW_config_ptr->CC_FlexRay_memory_base_address) + \                         (header_MB_ptr[3] / 2));        // Test if given data length is not zero, then read length from         if(Fr_data_length == 0)        {            Fr_data_length = (uint8)(header_MB_ptr[1] & 0x007F);   // Load the data payload length value from Frame header register        }                // Copy data        for(Fr_p = 0; Fr_p < Fr_data_length; Fr_p++)        {            Fr_CC_data_ptr[Fr_p] = Fr_data_ptr[Fr_p];   // Copy all items        }                // Set MB to commit        // Load MBCCSRn register and select only necessary bits        temp_value_1 = (Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] & 0xF900);        temp_value_1 |= FrMBCCSR_CMT;        Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;                // Attempt to unlock MB        // Load MBCCSRn register and select only necessary bits        temp_value_1 = (Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] & 0xF900);        temp_value_1 |= FrMBCCSR_LCKT;      // Trigger lock/unlock        Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_1;    }    else    {        // Clear Transmit Buffer Interrupt Flag            // Read MBCCSRn and select only necessary bits        temp_value_2 = (Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] & 0xF900);        temp_value_2 |= FrMBCCSR_MBIF;          // Set MBIF flag - clear TX MB interrupt flag         Fr_CC_reg_ptr[FrMBCCSR0 + Fr_MB_registers_offset_add_temp] = temp_value_2;  // Clear Transmit Buffer Interrupt Flag        return FR_TXMB_NO_ACCESS;       // The transmit MB has not been successfully locked    }    return FR_TXMB_UPDATED;                 // The transmit MB has been updated with new data}

 

 

Thank you in advance,

 

Best Regards,

Outcomes