If you want a CPU with exact instruction timings, then you'll need to use a simpler CPU, like one from the 1980's. That was the last time we could convert assembly instructions into exact clock cycles.
> Section 4.7 Instruction Timings in The E200Z0 Reference Manual (e200z0RM.pdf) is to brief on this,
There's 20 pages in that section, and I think it describes the timing pretty well.
All instructions (try to) execute at the rate of one instruction per clock. The exceptions are Multiply (1-4 clocks), divide (5-34 clocks) - both of these depend on the data they're being fed and the Load and Store multiple instructions.
Mispredicted branches take an extra clock. That's basically all you need to know about instruction timing.
I said "try to" because this all assumes the memory is fast enough to keep the CPU supplied with instructions and data and you're getting a good cache hit ratio. Get these wrong and the CPU can be stuck in wait-cycles waiting for the memory.
It also requires a smart compiler to re-order instruction sequences to "load early and execute late". The CPU doesn't stall on a load (unlike the ColdFire chip I'm working with) until another instruction tries to use the loaded data. Optimisation is very important here. So is data ordering. if you're reading data "with the cache" it goes a lot faster than reading "across cache lines" - like reading an array by columns instead of rows.
The CPU might be stalled for a long time reading or writing I/O registers. I don't know how many cycles these chips take to perform I/O but I've used ARM-based chips that the CPU with 200 wait-states to access an I/O port. The ColdFire V3 chip I'm using takes 18 clocks to write to a GPIO port and 33 clocks to do a "port |= bit" operation.
Anyone have GPIO read and write timing for the MPC chips?
Tom
